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16 条记录 (耗时 0.019 秒)

    Method of forming isolation trench with spacer formation
    4.
    发明授权
    Method of forming isolation trench with spacer formation 有权
    形成隔离沟的方法

    公开(公告)号：US07144785B2

    公开(公告)日：2006-12-05

    申请号：US10976869

    申请日：2004-11-01

    申请人： Srikanteswara Dakshina-Murthy ,  Douglas Bonser ,  Mark C. Kelling ,  Asuka Nomura

    发明人： Srikanteswara Dakshina-Murthy ,  Douglas Bonser ,  Mark C. Kelling ,  Asuka Nomura

    IPC分类号： H01L21/336

    CPC分类号： H01L21/76224

    摘要： A strained silicon semiconductor arrangement with a shallow trench isolation (STI) structure has a strained silicon (Si) layer formed on a silicon germanium (SiGe) layer. A trench extends through the Si layer into the SiGe layer, and sidewall spacers are employed that cover the entirety of the sidewalls within the trench in the SiGe layer. Following STI fill, polish and nitride stripping process steps, further processing can be performed without concern of the SiGe layer being exposed to a silicide formation process.

    摘要翻译： 具有浅沟槽隔离（STI）结构的应变硅半导体装置具有在硅锗（SiGe）层上形成的应变硅（Si）层。 沟槽穿过Si层延伸到SiGe层中，并且采用覆盖SiGe层中的沟槽内的整个侧壁的侧壁间隔物。 在STI填充，抛光和氮化物剥离工艺步骤之后，可以进行进一步处理，而不用关心SiGe层暴露于硅化物形成过程。

    Selective epitaxial growth for tunable channel thickness
    6.
    发明授权
    Selective epitaxial growth for tunable channel thickness 有权
    选择性外延生长可调谐通道厚度

    公开(公告)号：US07105399B1

    公开(公告)日：2006-09-12

    申请号：US11004951

    申请日：2004-12-07

    申请人： Srikanteswara Dakshina-Murthy ,  Douglas Bonser ,  Hans Van Meer ,  David Brown

    发明人： Srikanteswara Dakshina-Murthy ,  Douglas Bonser ,  Hans Van Meer ,  David Brown

    IPC分类号： H01L21/302 ,  H01L21/8238

    CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/84

    摘要： Gate electrodes with selectively tuned channel thicknesses are formed by selective epitaxial growth. Embodiments include forming shallow trench isolation regions in an SOI substrate, selectively removing the nitride stop layer and pad oxide layer in an exposed particular active region, and implementing selective epitaxial growth to increase the thickness of the semiconductor layer in the particular active region. Subsequently, the remaining nitride stop and pad oxide layers in other active regions are removed, gate dielectric layers formed, as by thermal oxidation, and the transistors completed.

    摘要翻译： 通过选择性外延生长形成具有选择性调谐的沟道厚度的栅极。 实施例包括在SOI衬底中形成浅沟槽隔离区域，选择性地去除暴露的特定有源区域中的氮化物阻挡层和衬垫氧化物层，以及实现选择性外延生长以增加特定有源区域中的半导体层的厚度。 随后，去除其它有源区中剩余的氮化物阻挡层和焊盘氧化物层，如通过热氧化形成栅介电层，并完成晶体管。

    FORMATION OF FINFET GATE SPACER
    8.
    发明申请
    FORMATION OF FINFET GATE SPACER 有权
    形成FINFET GATE SPACER

    公开(公告)号：US20110198673A1

    公开(公告)日：2011-08-18

    申请号：US12707291

    申请日：2010-02-17

    申请人： Douglas Bonser ,  Catherine B. Labelle

    发明人： Douglas Bonser ,  Catherine B. Labelle

    IPC分类号： H01L29/423 ,  H01L21/28

    CPC分类号： H01L29/66795 ,  H01L29/785

    摘要： Gate spacers are formed in FinFETS having a bottom portion of a first material extending to the height of the fins, and a top portion of a second material extending above the fins. An embodiment includes forming a fin structure on a substrate, the fin structure having a height and having a top surface and side surfaces, forming a gate substantially perpendicular to the fin structure over a portion of the top and side surfaces, for example over a center portion, forming a planarizing layer over the gate, the fin structure, and the substrate, removing the planarizing layer from the substrate, gate, and fin structure down to the height of the fin structure, and forming spacers on the fin structure and on the planarizing layer, adjacent the gate.

    摘要翻译： 在具有延伸到翅片的高度的第一材料的底部的FinFETS中形成栅极间隔物，以及在鳍片上方延伸的第二材料的顶部。 一个实施例包括在衬底上形成翅片结构，翅片结构具有高度并具有顶表面和侧表面，在顶表面和侧表面的一部分上形成基本上垂直于鳍结构的栅极，例如在中心 在栅极上形成平坦化层，鳍结构和衬底，将平坦化层从衬底，栅极和鳍结构移除到翅片结构的高度，并且在翅片结构上和在翅片结构上形成间隔物 平坦化层，邻近门。

    CVD silicon carbide layer as a BARC and hard mask for gate patterning
    9.
    发明授权
    CVD silicon carbide layer as a BARC and hard mask for gate patterning 有权
    CVD碳化硅层作为BARC和用于栅极图案化的硬掩模

    公开(公告)号：US06653735B1

    公开(公告)日：2003-11-25

    申请号：US10209447

    申请日：2002-07-30

    申请人： Chih Yuh Yang ,  Douglas Bonser ,  Pei-Yuan Gao ,  Lu You

    发明人： Chih Yuh Yang ,  Douglas Bonser ,  Pei-Yuan Gao ,  Lu You

    IPC分类号： H01L2348

    CPC分类号： H01L21/0276 ,  H01L21/0332 ,  H01L21/32139

    摘要： A BARC comprising materials having a lower pinhole density than that of silicon oxynitride and materials having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of polysilicon than that of amorphous carbon is employed to reduce deformation of a pattern to be formed in a patternable layer. The patternable layer is formed over a substrate. A multi-layered anti-reflective coating is formed over the patternable layer. A photoresist pattern is formed on the coating. The coating may comprise an amorphous carbon layer formed over the patternable layer and a SiC layer having a lower pinhole density than the pinhole density of SiON formed over the amorphous carbon layer. The coating may also be formed over a polysilicon layer and comprise a thermal expansion buffer layer having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of polysilicon than that of amorphous carbon.

    摘要翻译： 使用包含具有比氮氧化硅更小的针孔密度的材料的BARC和具有比非晶碳更接近于多晶硅热膨胀系数的热膨胀系数的材料来减少将形成的图案的变形 可图案层。 可图案层形成在衬底上。 在可图案层上形成多层抗反射涂层。 在涂层上形成光致抗蚀剂图案。 涂层可以包括在可图案层上形成的无定形碳层和具有比在无定形碳层上形成的SiON的针孔密度小的针孔密度的SiC层。 涂层也可以形成在多晶硅层上，并且包括热膨胀缓冲层，其热膨胀系数比无定形碳的热膨胀系数更接近于多晶硅的热膨胀系数。