A non-volatile memory cell comprising a substrate, a charge-trapping layer, a control gate, a first conductive state of source and drain, a lightly doped region and a second conductive state of pocket-doped region. The charge-trapping layer and the control gate are disposed over the substrate. A dielectric layer is disposed between the substrate, the charge-trapping layer and the control gate. The source and drain are disposed in the substrate on each side of the charge-trapping layer. The lightly doped region is disposed on the substrate surface between the source and the charge-trapping layer. The pocket-doped region is disposed within the substrate between the drain and the charge-trapping layer. Because there are asymmetrical configuration and different doped conductive states of implant structures, the programming speed of the memory cell is increased, the neighboring cell disturb issue is prevented, and the area occupation of the bit line selection transistor is reduced.