A power-up detection circuit which operates in a stable way regardless of variation in PVT. The power-up detection circuit includes a bias circuit that generates a bias voltage in response to an external voltage, and a detection circuit that generates a detection signal in response to the bias voltage. The response speed of the bias circuit to the external voltage and the response speed of the detection circuit to the bias voltage vary depending upon process, voltage and temperature (PVT). Accordingly, the power-up detection circuit and semiconductor device including the same can operate in a stable manner regardless of variation in PVT.