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公开(公告)号：US12117489B2
公开(公告)日：2024-10-15
申请号：US17019239
申请日：2020-09-12
IPC分类号： G01R31/317 , G01R27/26 , G01R31/10 , H03B27/00 , H03L7/00
CPC分类号： G01R31/31727 , G01R27/2605 , G01R27/2617 , G01R31/10 , H03B27/00 , H03L7/00
摘要： A device for measuring characteristics of a wafer is provided. The device includes a first circuit on the wafer and having a first number of parallelly connected oscillators, and a second circuit on the wafer and having the first number of parallelly connected oscillators; wherein a first portion of the second circuit is disconnected from a second portion of the second circuit.
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2.发明授权公开(公告)号：US12111786B2
公开(公告)日：2024-10-08
申请号：US17338512
申请日：2021-06-03
申请人： Intel Corporation
发明人： Jihwan Kim , Ajay Balankutty , Sandipan Kundu , Stephen Kim , Frank O'Mahony , Kai Yu , Bong Chan Kim
IPC分类号： G06F13/42 , G06F1/06 , G06F1/10 , H03K17/687 , H03L7/00
CPC分类号： G06F13/4291 , G06F1/06 , G06F1/10 , H03K17/6872 , H03K17/6874 , H03L7/00
摘要： An apparatus enables a high-bandwidth 4-way data serializing (4:1 serializer) digital-to-analog converter. The apparatus uses active inductor-based bandwidth extension technique for two-stage driver enabling design of quarter-rate 4-way data serializing transmitter. The 4:1 serializer output bandwidth is extended by gate-resistor-peaked n-type transistor load working as an active inductor. A current steering switch with current source is used as the final driver. The 4:1 serializer includes a pulse width tuning technique with tunable ground voltage on the ground terminal of a pulse generator to tune an effective threshold voltage of the pulse generator. A Bessel-like LC filter is coupled to an output of the 4:1 serializer. The filter includes shunt peaking paths that provide zeros, which natively cancel large parasitic capacitance at a shunt peaking node. As such, active and passive devices including driver circuitry, ESD diodes, and any other sensing circuitry are flexibly added on any LC filter nodes.
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公开(公告)号：US20240305301A1
公开(公告)日：2024-09-12
申请号：US18668282
申请日：2024-05-20
IPC分类号： H03L7/08 , G01R31/317 , G04F10/00 , H03L7/00
CPC分类号： H03L7/08 , G01R31/31707 , G01R31/31711 , G04F10/005 , H03L7/00
摘要： A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.
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公开(公告)号：US12063046B2
公开(公告)日：2024-08-13
申请号：US18063809
申请日：2022-12-09
CPC分类号： H03L7/0991 , H03D13/001 , H03K3/12
摘要： Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.
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公开(公告)号：US11960320B2
公开(公告)日：2024-04-16
申请号：US18301669
申请日：2023-04-17
申请人： KIOXIA CORPORATION
发明人： Toshitada Saito , Akihisa Fujimoto
IPC分类号： H03L7/07 , G06F1/06 , G06F1/12 , G06F13/38 , G06F13/42 , H03L7/00 , H03L7/08 , H03L7/091 , H03L7/099 , H04L7/00 , H04L7/033 , H04L25/08 , H04L25/14
CPC分类号： G06F1/06 , G06F1/12 , G06F13/38 , G06F13/4282 , H03L7/00 , H03L7/07 , H03L7/0807 , H03L7/091 , H03L7/099 , H04L7/0004 , H04L7/033 , H04L25/085 , H04L25/14 , H04L7/0012
摘要： According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.
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6.发明公开公开(公告)号：US20240106437A1
公开(公告)日：2024-03-28
申请号：US18519866
申请日：2023-11-27
IPC分类号： H03L7/00
CPC分类号： H03L7/00
摘要： A synchronization method for multi-channel signals, a power supply module, an electronic device, and a power supply device. In the synchronization method for multi-channel signals, a first power supply module (700) is connected to a plurality of mutually isolated second power supply modules (800), allocates target data information and a target duration to each of the second power supply modules (800) according to total data information input by a user; and then the first power supply module (700) synchronously transmits a clock signal to each of the second power supply modules (800), so as to trigger each of the second power supply modules (800) to synchronously output a data signal corresponding to the target data information, and to control an output duration of the data signal to be equal to the target duration.
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公开(公告)号：US11916558B1
公开(公告)日：2024-02-27
申请号：US18080728
申请日：2022-12-13
发明人： Yong Xu , Boris Dimitrov Andreev , Vikas Mahendiyan , Yuxin Li , Anand Meruva , Jeffrey Mark Hinrichs
CPC分类号： H03L7/0812 , G06F1/12 , H03K19/20
摘要： A method for clock switching includes propagating a first clock signal through a first clock path, propagating a second clock signal through a second clock path, generating a first delay control signal based on the first clock signal, and generating a second delay control signal based on the second clock signal. The method also includes, in a first mode, coupling the first clock path to a delay circuit and inputting the first delay control signal to a control input of the delay circuit. The method also includes, in a second mode, coupling the second clock path to the delay circuit and inputting the second delay control signal to the control input of the delay circuit.
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公开(公告)号：US20240063801A1
公开(公告)日：2024-02-22
申请号：US18498801
申请日：2023-10-31
发明人： Xiangye WEI , Liming XIU
CPC分类号： H03L7/00 , H03K5/135 , H03K23/542 , H03K19/20
摘要： An integrated circuit is provided. The integrated circuit includes: a clock source configured to: generate a clock signal of the integrated circuit; at least two functional circuits; and at least two clock generators corresponding to the functional circuits and configured to: determine initial phases of the corresponding functional circuits, and generate clock signals of the functional circuits based on the clock signal of the integrated circuit and the initial phases, so as to keep the clock signals of all the functional circuits synchronized, wherein the initial phases are determined based on transmission distances, over which the clock signal of the integrated circuit is transmitted from the clock source to the functional circuits, and loads of the functional circuits.
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公开(公告)号：US11770101B2
公开(公告)日：2023-09-26
申请号：US17723103
申请日：2022-04-18
CPC分类号： H03B5/1243 , H03B5/1218 , H03B5/1228 , H03B5/1262 , H03B5/1265 , H03B5/1293 , H03B5/1296 , H03F1/565 , H03F3/193 , H03F3/245 , H03F3/72 , H03L7/00 , H04B1/44 , H03B2201/0266
摘要： The invention relates to a radio frequency oscillator, the radio frequency oscillator comprising a resonator circuit being resonant at an excitation of the resonator circuit in a differential mode and at an excitation of the resonator circuit in a common mode, wherein the resonator circuit has a differential mode resonance frequency at the excitation in the differential mode, and wherein the resonator circuit has a common mode resonance frequency at the excitation in the common mode, a first excitation circuit being configured to excite the resonator circuit in the differential mode to obtain a differential mode oscillator signal oscillating at the differential mode resonance frequency, and a second excitation circuit being configured to excite the resonator circuit in the common mode to obtain a common mode oscillator signal oscillating at the common mode resonance frequency.
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10.发明公开公开(公告)号：US20230266385A1
公开(公告)日：2023-08-24
申请号：US18157344
申请日：2023-01-20
申请人： Rambus Inc.
发明人： Frederick A. Ware
IPC分类号： G01R31/28 , G01R31/317 , G11C29/02 , G11C29/12 , G11C29/16 , G11C29/50 , G01R31/26 , H03L7/00
CPC分类号： G01R31/2882 , G01R31/31726 , G11C29/022 , G11C29/12015 , G11C29/16 , G11C29/50012 , G01R31/2607 , H03L7/00 , G11C2029/0401
摘要： A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The semiconductor IC device further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.
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