- 专利标题: Method of manufacturing a semiconductor device and semiconductor device obatined with such a method
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申请号: US10539224申请日: 2003-12-15
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公开(公告)号: US20060152086A1公开(公告)日: 2006-07-13
- 发明人: Vincent Venezia , Charles Dachs , Jacob Hooker , Marcus Van Dal
- 申请人: Vincent Venezia , Charles Dachs , Jacob Hooker , Marcus Van Dal
- 申请人地址: NL Eindhoven 5621
- 专利权人: Koninklijke Philips Electronics N.V.
- 当前专利权人: Koninklijke Philips Electronics N.V.
- 当前专利权人地址: NL Eindhoven 5621
- 国际申请: PCT/IB03/06009 WO 20031215
- 主分类号: H02B1/24
- IPC分类号: H02B1/24
摘要:
The invention relates to a method of manufacturing a semiconductor device (10) with a field effect transistor, in which method a semiconductor body (1) of a semiconductor material is provided, at a surface thereof, with a source region (2) and a drain region (3) and with a gate region (4) between the source region (2) and the drain region (3), which gate region comprises a semiconductor region (4A) of a further semiconductor material that is separated from the surface of the semiconductor body (1) by a gate dielectric (5), and with spacers (6) adjacent to the gate region (4), for forming the source and drain regions (2,3), in which method the source region (2) and the drain region (3) are provided with a metal layer (7) which is used to form a compound (8) of the metal and the semiconductor material, and the gate region (4) is provided with a metal layer (7) which is used to form a compound (8) of the metal and the further semiconductor material. The known method in which different metal layers are used to silicidate source and drain regions and gate regions (2,3,4) has several drawbacks. A method according to the invention is characterized in that before the spacers (6) are formed, a sacrificial region (4B) of a material that may be selectively etched with respect to the semiconductor region (4A) is deposited on top of the semiconductor region (4A), and after the spacers (6) have been formed, the sacrificial layer (4B) is removed by etching, and after removal of the sacrificial layer (4B), a single metal layer (7) is deposited contacting the source, drain and gate regions (2,3,4). This method is on the one hand very simple as it requires only a single metal layer and few, straight-forward steps and it is compatible with existing (silicon) technology, and on the other hand it results in a (MOS)FET which does not suffer from a depletion layer effect in the fully silicided gate (4).
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