公开(公告)号：US20060152086A1

公开(公告)日：2006-07-13

申请号：US10539224

申请日：2003-12-15

申请人： Vincent Venezia ,  Charles Dachs ,  Jacob Hooker ,  Marcus Van Dal

发明人： Vincent Venezia ,  Charles Dachs ,  Jacob Hooker ,  Marcus Van Dal

IPC分类号： H02B1/24

CPC分类号： H01L29/41783 ,  H01L21/26586 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/1045 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  Y10T307/74

摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a field effect transistor, in which method a semiconductor body (1) of a semiconductor material is provided, at a surface thereof, with a source region (2) and a drain region (3) and with a gate region (4) between the source region (2) and the drain region (3), which gate region comprises a semiconductor region (4A) of a further semiconductor material that is separated from the surface of the semiconductor body (1) by a gate dielectric (5), and with spacers (6) adjacent to the gate region (4), for forming the source and drain regions (2,3), in which method the source region (2) and the drain region (3) are provided with a metal layer (7) which is used to form a compound (8) of the metal and the semiconductor material, and the gate region (4) is provided with a metal layer (7) which is used to form a compound (8) of the metal and the further semiconductor material. The known method in which different metal layers are used to silicidate source and drain regions and gate regions (2,3,4) has several drawbacks. A method according to the invention is characterized in that before the spacers (6) are formed, a sacrificial region (4B) of a material that may be selectively etched with respect to the semiconductor region (4A) is deposited on top of the semiconductor region (4A), and after the spacers (6) have been formed, the sacrificial layer (4B) is removed by etching, and after removal of the sacrificial layer (4B), a single metal layer (7) is deposited contacting the source, drain and gate regions (2,3,4). This method is on the one hand very simple as it requires only a single metal layer and few, straight-forward steps and it is compatible with existing (silicon) technology, and on the other hand it results in a (MOS)FET which does not suffer from a depletion layer effect in the fully silicided gate (4).

公开(公告)号：US08614112B2

公开(公告)日：2013-12-24

申请号：US12896518

申请日：2010-10-01

申请人： Keh-Chiang Ku ,  Chia-Ying Liu ,  Hsin-Chih Tai ,  Vincent Venezia

发明人： Keh-Chiang Ku ,  Chia-Ying Liu ,  Hsin-Chih Tai ,  Vincent Venezia

IPC分类号： H01L31/0232 ,  H01L31/18

CPC分类号： H01L27/1464 ,  H01L27/14698

摘要： A method of fabricating a backside-illuminated pixel. The method includes forming frontside components of the pixel on or in a front side of a substrate, the frontside components including a photosensitive region of a first polarity. The method further includes forming a pure dopant region of a second polarity on a back side of the substrate, applying a laser pulse to the backside of the substrate to melt the pure dopant region, and recrystallizing the pure dopant region to form a backside doped layer. Corresponding apparatus embodiments are disclosed and claimed.

摘要翻译： 背面照明像素的制造方法。 该方法包括在衬底的前侧或其前侧形成像素的前侧分量，前侧部件包括第一极性的感光区域。 该方法还包括在衬底的背面形成具有第二极性的纯掺杂剂区域，向衬底的背面施加激光脉冲以熔化纯掺杂剂区域，并重结晶纯掺杂剂区域以形成背面掺杂层 。 相应的装置实施例被公开和要求保护。

公开(公告)号：US08569856B2

公开(公告)日：2013-10-29

申请号：US13288731

申请日：2011-11-03

申请人： Yin Qian ,  Hsin-Chih Tai ,  Keh-Chiang Ku ,  Vincent Venezia ,  Duli Mao ,  Wei Zheng ,  Howard E. Rhodes

发明人： Yin Qian ,  Hsin-Chih Tai ,  Keh-Chiang Ku ,  Vincent Venezia ,  Duli Mao ,  Wei Zheng ,  Howard E. Rhodes

IPC分类号： H01L21/00

CPC分类号： H01L23/481 ,  H01L21/6835 ,  H01L23/522 ,  H01L24/05 ,  H01L27/14636 ,  H01L27/1464 ,  H01L2221/6835 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05567 ,  H01L2924/00014 ,  H01L2924/12043 ,  H01L2224/05552 ,  H01L2924/00

摘要： Embodiments of a semiconductor device that includes a semiconductor substrate and a cavity disposed in the semiconductor substrate that extends at least from a first side of the semiconductor substrate to a second side of the semiconductor substrate. The semiconductor device also includes an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity. A conductive layer including a bonding pad is disposed over the insulation layer. The conductive layer extends into the cavity and connects to a metal stack disposed below the second side of the semiconductor substrate. A through silicon via pad is disposed below the second side of the semiconductor substrate and connected to the metal stack. The through silicon via pad is position to accept a through silicon via.

摘要翻译： 半导体器件的实施例包括半导体衬底和设置在半导体衬底中的至少从半导体衬底的第一侧至半导体衬底的第二侧延伸的空腔。 半导体器件还包括设置在半导体衬底的第一侧上并涂覆空腔的侧壁的绝缘层。 包括接合焊盘的导电层设置在绝缘层上。 导电层延伸到空腔中并且连接到设置在半导体衬底的第二侧下方的金属叠层。 贯穿硅通孔焊盘设置在半导体衬底的第二侧下方并连接到金属堆叠。 贯穿硅通孔焊盘的位置是接受硅通孔。

公开(公告)号：US08482639B2

公开(公告)日：2013-07-09

申请号：US12028590

申请日：2008-02-08

申请人： Hsin-Chih Tai ,  Vincent Venezia ,  Duli Mao ,  Howard E. Rhodes

发明人： Hsin-Chih Tai ,  Vincent Venezia ,  Duli Mao ,  Howard E. Rhodes

IPC分类号： H04N9/64

CPC分类号： H01L27/14621 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14685

摘要： An imaging sensor pixel array includes a semiconductor substrate, a plurality of active pixels and at least one black reference pixel. The plurality of active pixels are disposed in the semiconductor substrate for capturing an image. Each of the active pixels includes a first region for receiving light including a p-n junction for accumulating an image charge and active pixel circuitry coupled to the first region to readout the image charge. The black reference pixel is also disposed within the semiconductor substrate for generating a black level reference value. The black reference pixel includes a second region for receiving light without a p-n junction and black pixel circuitry coupled to the photodiode region without the p-n junction to readout a black level reference signal.

公开(公告)号：US08426796B2

公开(公告)日：2013-04-23

申请号：US13619879

申请日：2012-09-14

申请人： Duli Mao ,  Hsin-Chih Tai ,  Vincent Venezia ,  Howard E. Rhodes ,  Sohei Manabe

发明人： Duli Mao ,  Hsin-Chih Tai ,  Vincent Venezia ,  Howard E. Rhodes ,  Sohei Manabe

IPC分类号： H01L27/146

CPC分类号： H04N5/35509 ,  H04N5/3559 ,  H04N5/3597 ,  H04N5/37452 ,  H04N5/376

摘要： An image sensor includes a pixel array, a bit line, a supplemental capacitance node line, and a control circuit. The pixel array includes a plurality of pixel cells each including a floating diffusion (“FD”) node and a photosensitive element coupled to selectively transfer image charge to the FD node. The bit line is coupled to selectively conduct image data output from a first group of the pixel cells. The supplemental capacitance node line is coupled to the FD node of a second group of the pixel cells different from the first group. The control circuit is coupled to the supplemental capacitance node line to selectively increase the potential at the FD node of each of the pixel cells of the second group by selectively asserting a FD boost signal on the supplemental capacitance node line.

摘要翻译： 图像传感器包括像素阵列，位线，补充电容节点线和控制电路。 像素阵列包括多个像素单元，每个像素单元包括浮动扩散（“FD”）节点和耦合以选择性地将图像电荷传送到FD节点的感光元件。 位线被耦合以选择性地进行从第一组像素单元输出的图像数据。 辅助电容节点线耦合到与第一组不同的第二组像素单元的FD节点。 控制电路通过选择性地在辅助电容节点线上确定FD升压信号来耦合到辅助电容节点线，以选择性地增加第二组的每个像素单元的FD节点的电位。

公开(公告)号：US20130092982A1

公开(公告)日：2013-04-18

申请号：US13273026

申请日：2011-10-13

申请人： Gang Chen ,  Sing-Chung Hu ,  Hsin-Chih Tai ,  Duli Mao ,  Manoj Bikumandla ,  Wei Zheng ,  Yin Qian ,  Zhibin Xiong ,  Vincent Venezia ,  Keh-Chiang Ku ,  Howard E. Rhodes

发明人： Gang Chen ,  Sing-Chung Hu ,  Hsin-Chih Tai ,  Duli Mao ,  Manoj Bikumandla ,  Wei Zheng ,  Yin Qian ,  Zhibin Xiong ,  Vincent Venezia ,  Keh-Chiang Ku ,  Howard E. Rhodes

IPC分类号： H01L27/148 ,  H01L31/18 ,  H01L31/101

CPC分类号： H01L27/14616 ,  H01L27/14689

摘要： Embodiments of an image sensor pixel that includes a photosensitive element, a floating diffusion region, and a transfer device. The photosensitive element is disposed in a substrate layer for accumulating an image charge in response to light. The floating diffusion region is dispose in the substrate layer to receive the image charge from the photosensitive element. The transfer device is disposed between the photosensitive element and the floating diffusion region to selectively transfer the image charge from the photosensitive element to the floating diffusion region. The transfer device includes a buried channel device including a buried channel gate disposed over a buried channel dopant region. The transfer device also includes a surface channel device including a surface channel gate disposed over a surface channel region. The surface channel device is in series with the buried channel device. The surface channel gate has the opposite polarity of the buried channel gate.

摘要翻译： 包括感光元件，浮动扩散区域和转印装置的图像传感器像素的实施例。 感光元件设置在基板层中，用于响应于光积累图像电荷。 浮动扩散区域设置在衬底层中以从感光元件接收图像电荷。 转移装置设置在感光元件和浮动扩散区域之间以选择性地将图像电荷从感光元件转移到浮动扩散区域。 传输装置包括掩埋沟道器件，其包括设置在掩埋沟道掺杂区域上的掩埋沟道栅极。 转移装置还包括表面通道装置，其包括设置在表面通道区域上的表面通道门。 表面通道装置与掩埋通道装置串联。 表面沟道栅极具有与掩埋沟道栅极相反的极性。

公开(公告)号：US08405748B2

公开(公告)日：2013-03-26

申请号：US12837870

申请日：2010-07-16

申请人： Duli Mao ,  Hsin-Chih Tai ,  Vincent Venezia ,  Yin Qian ,  Howard E. Rhodes

发明人： Duli Mao ,  Hsin-Chih Tai ,  Vincent Venezia ,  Yin Qian ,  Howard E. Rhodes

IPC分类号： H04N3/14

CPC分类号： H04N5/3696 ,  H01L27/14621 ,  H01L27/1464 ,  H04N9/04

摘要： Embodiments of an apparatus comprising a pixel array comprising a plurality of macropixels. Each macropixel includes a pair of first pixels each including a color filter for a first color, the first color being one to which pixels are most sensitive, a second pixel including a color filter for a second color, the second color being one to which the pixels are least sensitive and a third pixel including a color filter for a third color, the third color being one to which pixels have a sensitivity between the least sensitive and the most sensitive, wherein the first pixels each occupy a greater proportion of the light-collection area of the macropixel than either the second pixel or the third pixel. Corresponding process and system embodiments are disclosed and claimed.

摘要翻译： 包括包括多个宏像素的像素阵列的装置的实施例。 每个宏像素包括一对第一像素，每个第一像素包括用于第一颜色的滤色器，第一颜色是像素最敏感的一个，第二像素包括用于第二颜色的滤色器，第二颜色是 像素是最不灵敏的，并且第三像素包括用于第三颜色的滤色器，第三颜色是像素在最不灵敏和最敏感之间具有灵敏度的一个，其中第一像素每个占据较大比例的发光元件， 大小像素的收集区域比第二像素还是第三像素。 公开和要求保护相应的过程和系统实施例。

公开(公告)号：US08338856B2

公开(公告)日：2012-12-25

申请号：US12853803

申请日：2010-08-10

申请人： Hsin-Chih Tai ,  Howard E. Rhodes ,  Wei Zheng ,  Vincent Venezia ,  Yin Qian ,  Duli Mao

发明人： Hsin-Chih Tai ,  Howard E. Rhodes ,  Wei Zheng ,  Vincent Venezia ,  Yin Qian ,  Duli Mao

IPC分类号： H01L31/0328

CPC分类号： H01L27/1464 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14638

摘要： A backside illuminated (“BSI”) complementary metal-oxide semiconductor (“CMOS”) image sensor includes a photosensitive region disposed within a semiconductor layer and a stress adjusting layer. The photosensitive region is sensitive to light incident on a backside of the BSI CMOS image sensor to collect an image charge. The stress adjusting layer is disposed on a backside of the semiconductor layer to establish a stress characteristic that encourages photo-generated charge carriers to migrate towards the photosensitive region.

摘要翻译： 背面照明（BSI）互补金属氧化物半导体（CMOS）图像传感器包括设置在半导体层和应力调整层内的感光区域。 感光区域对入射到BSI CMOS图像传感器背面的光敏感，以收集图像电荷。 应力调整层设置在半导体层的背面，以建立一种应力特性，该应力特性促使光生电荷载流子迁移到光敏区域。

公开(公告)号：US08330195B2

公开(公告)日：2012-12-11

申请号：US12967759

申请日：2010-12-14

申请人： Vincent Venezia ,  Ashish Shah ,  Rongsheng Yang ,  Duli Mao ,  Yin Qian ,  Hsin-Chih Tai ,  Howard E. Rhodes

发明人： Vincent Venezia ,  Ashish Shah ,  Rongsheng Yang ,  Duli Mao ,  Yin Qian ,  Hsin-Chih Tai ,  Howard E. Rhodes

IPC分类号： H01L31/062

CPC分类号： H01L27/1463 ,  H01L27/14601

摘要： An image sensor pixel includes a substrate, a first epitaxial layer, a collector layer, a second epitaxial layer and a light collection region. The substrate is doped to have a first conductivity type. The first epitaxial layer is disposed over the substrate and doped to have the first conductivity type as well. The collector layer is selectively disposed over at least a portion of the first epitaxial layer and doped to have a second conductivity type. The second epitaxial layer is disposed over the collector layer and doped to have the first conductivity type. The light collection region collects photo-generated charge carriers and is disposed within the second epitaxial layer. The light collection region is also doped to have the second conductivity type.

摘要翻译： 图像传感器像素包括基板，第一外延层，集电极层，第二外延层和光收集区域。 衬底被掺杂以具有第一导电类型。 第一外延层设置在衬底上并掺杂以具有第一导电类型。 集电极层选择性地设置在第一外延层的至少一部分上并被掺杂以具有第二导电类型。 第二外延层设置在集电极层上并掺杂以具有第一导电类型。 光收集区域收集光生电荷载流子并且设置在第二外延层内。 光收集区域也被掺杂以具有第二导电类型。

公开(公告)号：US20120302000A1

公开(公告)日：2012-11-29

申请号：US13566638

申请日：2012-08-03

申请人： Duli Mao ,  Hsin-Chih Tai ,  Vincent Venezia ,  Yin Qian ,  Howard E. Rhodes

发明人： Duli Mao ,  Hsin-Chih Tai ,  Vincent Venezia ,  Yin Qian ,  Howard E. Rhodes

IPC分类号： H01L31/0232

CPC分类号： H01L27/14698 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689

摘要： A technique for fabricating an image sensor including a pixel circuitry region and a peripheral circuitry region includes fabricating front side components on a front side of the image sensor. A dopant layer is implanted on a backside of the image sensor. A anti-reflection layer is formed on the backside and covers a first portion of the dopant layer under the pixel circuitry region while exposing a second portion of the dopant layer under the peripheral circuitry region. The first portion of the dopant layer is laser annealed from the backside of the image sensor through the anti-reflection layer. The anti-reflection layer increases a temperature of the first portion of the dopant layer during the laser annealing.

摘要翻译： 一种用于制造包括像素电路区域和外围电路区域的图像传感器的技术包括在图像传感器的正面上制造前侧部件。 掺杂剂层植入图像传感器的背面。 在背面形成防反射层，并且在像素电路区域下方覆盖掺杂剂层的第一部分，同时在外围电路区域下方暴露掺杂剂层的第二部分。 掺杂剂层的第一部分通过抗反射层从图像传感器的背面激光退火。 抗反射层在激光退火期间增加掺杂剂层的第一部分的温度。