If a data processing system (10) implements more than one instruction set within a single processor (12), then program portions encoded using a first instruction set will need to be able to call program portions encoded using a second instruction set. This switching between instruction sets requires that the processor (12) be informed when instruction execution is switching between the plurality of instruction sets. A solution was needed that would allow program portions to freely intermix their usage of different instruction sets with no prior knowledge by the software programmer as to which instruction set is used for which program portion. In one embodiment, instruction address attribute (106) in address mapping circuitry (32) may be used to inform instruction decode unit (46) of processor (12) when instruction execution is switching between the plurality of instruction sets.