公开(公告)号：US20070266217A1

公开(公告)日：2007-11-15

申请号：US11382900

申请日：2006-05-11

Applicant: William Moyer ,  Jeffrey Scott

Inventor： William Moyer ,  Jeffrey Scott

IPC: G06F12/00

CPC classification number: G06F12/0804 ,  G06F9/30043 ,  G06F9/30181 ,  G06F9/3824 ,  G06F12/0888

Abstract: A processing system and method performs allocation of memory cache lines in response to a cache write miss. A processor receives a plurality of data processing instructions. A first store instruction for storing data in a system memory at a predetermined address is decoded by decoding a first specifier within the first store instruction. The first specifier determines an allocation policy for the first store instruction wherein the allocation policy determines whether to store data within the cache when the predetermined address is not within the cache. Additional store instructions are decoded. For example, a second specifier determines an allocation policy for a second store instruction. The specifier in each of the store instructions may be implemented in various forms to provide a policy indicator for each store instruction. No allocation policy may also be established on a per-access basis.

Abstract translation: 处理系统和方法响应于高速缓存写入未命中而执行存储器高速缓存行的分配。 处理器接收多个数据处理指令。 通过对第一存储指令内的第一说明符进行解码来解码用于将数据存储在预定地址的系统存储器中的第一存储指令。 第一说明符确定第一存储指令的分配策略，其中当预定地址不在高速缓存内时，分配策略确定是否在高速缓存中存储数据。 额外的存储指令被解码。 例如，第二说明符确定第二存储指令的分配策略。 每个存储指令中的说明符可以以各种形式实现，以为每个存储指令提供策略指示符。 也可以在每个访问的基础上建立分配策略。

公开(公告)号：US20070260863A1

公开(公告)日：2007-11-08

申请号：US11381284

申请日：2006-05-02

Applicant: William Moyer ,  Gary Whisenhunt

Inventor： William Moyer ,  Gary Whisenhunt

IPC: G06F9/44

CPC classification number: G06F9/4843 ,  G06F2209/507

Abstract: An integrated circuit (10) has a conditional yield instruction (305) which may be used to conditionally yield execution of a currently active thread based on priority and status of other threads. In one embodiment, an I bit 304 may be used to designate whether the priority selection bits (50) are stored in the instruction itself. If the priority selection bits (50) are not stored in the instruction itself, a portion of the instruction (302) may be used to store a location indicator which indicates where the priority selection bits (50) are located (e.g. register file 22).

Abstract translation: 集成电路（10）具有条件收益率指令（305），其可以用于基于其他线程的优先级和状态有条件地产生当前活动线程的执行。 在一个实施例中，可以使用I位304来指示优先级选择位（50）是否存储在指令本身中。 如果优先选择位（50）未被存储在指令本身中，则指令（302）的一部分可以用于存储指示优先级选择位（50）位于哪里的位置指示符（例如寄存器文件22） 。

公开(公告)号：US20070255924A1

公开(公告)日：2007-11-01

申请号：US11413422

申请日：2006-04-28

Applicant: William Moyer ,  Ray Marshall ,  Richard Soja

Inventor： William Moyer ,  Ray Marshall ,  Richard Soja

IPC: G06F12/00

CPC classification number: G06F12/1027

Abstract: In a processor having an address translation table, a method includes providing a logical address and control signal. When the control signal has a first value, a first physical address is provided corresponding to the logical address, and when the control signal has a second value, a second physical address is provided. The first physical address and the second physical address are stored in at least one valid entry of the address translation table. In one case, the first physical address is stored in a first valid entry having a tag field which matches the logical address and the second physical address is stored in a second valid entry having a tag field which matches the logical address. Alternatively, the first physical address is stored in a first field of a first valid entry and the second physical address is stored in a second field of the first valid entry.

Abstract translation: 在具有地址转换表的处理器中，一种方法包括提供逻辑地址和控制信号。 当控制信号具有第一值时，对应于逻辑地址提供第一物理地址，并且当控制信号具有第二值时，提供第二物理地址。 第一物理地址和第二物理地址存储在地址转换表的至少一个有效条目中。 在一种情况下，第一物理地址存储在具有与逻辑地址匹配的标签字段的第一有效条目中，并且第二物理地址被存储在具有与逻辑地址匹配的标签字段的第二有效条目中。 或者，第一物理地址存储在第一有效条目的第一字段中，并且第二物理地址存储在第一有效条目的第二字段中。

公开(公告)号：US20070234017A1

公开(公告)日：2007-10-04

申请号：US11392383

申请日：2006-03-29

Applicant: William Moyer

Inventor： William Moyer

IPC: G06F9/44

CPC classification number: G06F11/36

Abstract: A method includes generating an instruction address value in response to an instruction source event. The method further includes selectively generating a breakpoint request based on the instruction source event and responsive to a comparison of the instruction address value to a breakpoint address value. In one embodiment, selectively generating a breakpoint request includes comparing the instruction source event to an instruction source event type, comparing the instruction address value to a breakpoint address value, and generating the breakpoint request responsive to a match between the first instruction source event type and the instruction source event and a match between the instruction address value and the breakpoint address value.

Abstract translation: 一种方法包括响应于指令源事件产生指令地址值。 该方法还包括基于指令源事件选择性地生成断点请求，并且响应于指令地址值与断点地址值的比较。 在一个实施例中，选择性地产生断点请求包括将指令源事件与指令源事件类型进行比较，将指令地址值与断点地址值进行比较，以及响应于第一指令源事件类型和 指令源事件和指令地址值与断点地址值之间的匹配。

公开(公告)号：US20070180518A1

公开(公告)日：2007-08-02

申请号：US11343454

申请日：2006-01-31

Applicant: William Moyer

Inventor： William Moyer

IPC: G06F12/14

CPC classification number: G06F12/1483

Abstract: A method includes determining, at a first requesting component of an integrated circuit device, a first key value based on a first set of one or more bits of a first address associated with a first access request of the first requesting component. The method further includes transmitting the first key value from the first requesting component to a resource component of the integrated circuit device. The method also includes determining, at the resource component, an authorization of the first access request based on the first key value and a second set of one or more bits of the first address.

Abstract translation: 一种方法包括：在集成电路设备的第一请求组件处，基于与第一请求组件的第一访问请求相关联的第一地址的一个或多个位的第一集合来确定第一密钥值。 该方法还包括将第一密钥值从第一请求组件传输到集成电路设备的资源组件。 所述方法还包括在所述资源组件的基础上，基于所述第一密钥值和所述第一地址的一个或多个比特的第二组确定所述第一访问请求的授权。

公开(公告)号：US20060271919A1

公开(公告)日：2006-11-30

申请号：US11140310

申请日：2005-05-27

Applicant: William Moyer

Inventor： William Moyer

IPC: G06F9/45

CPC classification number: G06F11/3648

Abstract: A system for obtaining translation information from a data processing system transparent to the operation of a processor core of the data processing system. In one embodiment, the processor includes a processor core and memory management circuitry. The memory management circuitry stores translation information. The data processing system includes debugging circuitry for obtaining translation information stored in the memory management circuitry and for providing that information externally.

Abstract translation: 一种用于从对数据处理系统的处理器核心的操作透明的数据处理系统获得翻译信息的系统。 在一个实施例中，处理器包括处理器核心和存储器管理电路。 存储器管理电路存储翻译信息。 数据处理系统包括调试电路，用于获得存储在存储器管理电路中的翻译信息，并用于从外部提供该信息。

公开(公告)号：US20060230315A1

公开(公告)日：2006-10-12

申请号：US11094593

申请日：2005-03-30

Applicant: William Moyer

Inventor： William Moyer

IPC: G06F11/00

CPC classification number: G06F11/1004

Abstract: In accordance with one technique, a first plurality of values associated with data transfers between a processor and a memory is received at the processor and at least a subset of the first plurality of values are accumulated in one or more accumulators. The one or more accumulators are accessed to obtain a first accumulated value and the first accumulated value is compared with a first expected accumulated value. In accordance with a second technique, a first plurality of load operations are performed at a processor to access data values stored in a first sequence of fields of a memory. The data values are accumulated in one or more accumulators of the processor to generate a first accumulated value and it is determined whether the memory has been corrupted based on a comparison of the first accumulated value to a first expected accumulation value.

公开(公告)号：US20060195721A1

公开(公告)日：2006-08-31

申请号：US11065898

申请日：2005-02-25

Applicant: William Moyer ,  John Vaglica

Inventor： William Moyer ,  John Vaglica

IPC: G06F11/00

CPC classification number: G06F11/3648

Abstract: A data processing system (10) has a system debug module (19) coupled to a processor (12) for performing system debug functions. Located within the system, and preferably within the processor, is debug circuitry (32) that selectively provides debug information related to the processor. The circuitry identifies which of a plurality of registers (26) is sourcing the debug information. A user-determinable enable and disable mechanism that is correlated to some or all of the registers sourcing the debug information specifies whether to enable or disable the providing of the debug information. In one form a single bit functions as the mechanism for each correlated register. Debug operations including breakpoints, tracing, watchpoints, halting, event counting and others are qualified to enhance system debug. The registers may be included in a programmer's model and can be compliant with one or more industry debug related standards.

Abstract translation: 数据处理系统（10）具有耦合到处理器（12）的用于执行系统调试功能的系统调试模块（19）。 位于系统内，并且优选地在处理器内的是调试电路（32），其选择性地提供与处理器相关的调试信息。 电路识别多个寄存器（26）中的哪一个正在提供调试信息。 与源自调试信息的一些或所有寄存器相关联的用户可确定的启用和禁用机制指定是否启用或禁用提供调试信息。 在一种形式中，单个位用作每个相关寄存器的机制。 包括断点，跟踪，观察点，停止，事件计数等的调试操作有资格加强系统调试。 寄存器可能包含在程序员模型中，并且可以符合一个或多个行业调试相关标准。

公开(公告)号：US20060064445A1

公开(公告)日：2006-03-23

申请号：US10944310

申请日：2004-09-17

Applicant: William Moyer

Inventor： William Moyer

IPC: G06F15/00

CPC classification number: G06F9/30149 ,  G06F9/30032 ,  G06F9/30167

Abstract: A data processing system uses a data processor instruction that forms an immediate value. The data processing instruction uses a first field as a portion of the immediate value. A second field of the data processing instruction determines a positional location of the portion of the immediate value within the immediate value. A bit value in a third field of the data processing instruction is used to determine a remainder of the immediate value.

Abstract translation: 数据处理系统使用形成立即值的数据处理器指令。 数据处理指令使用第一个字段作为立即值的一部分。 数据处理指令的第二个字段确定立即数值中该立即值的部分的位置位置。 数据处理指令的第三个字段中的位值用于确定立即值的余数。

公开(公告)号：US20050273544A1

公开(公告)日：2005-12-08

申请号：US11203935

申请日：2005-08-15

Applicant: Michael Fitzsimmons ,  William Moyer ,  Brett Murdock

Inventor： Michael Fitzsimmons ,  William Moyer ,  Brett Murdock

IPC: G06F13/00 ,  G06F13/40

CPC classification number: G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

Abstract: A crossbar switch (12) arbitrates for access from multiple bus masters (14, 16, 18, 20 and 22) to multiple addressed slave ports (3 and 4) that have overlapping address ranges. In one form, the address ranges are the same address range. The crossbar switch (12) uses shared slave port control circuitry (48), configuration registers (46) and slave port arbiter logic (34, 36, 38, 40, 42 and 44) to arbitrate for access when all the addressed ports are busy. A determination is made as to whether new access requests are higher or lower in priority than existing accesses. A determination on where to direct a new access request is made based upon a prediction of which of certain multiple accesses will complete first based on various factors including the number of data beats requested as well as wait state information. In one mode, the wait state information is determined dynamically.

Abstract translation: 交叉开关（12）仲裁用于从多个总线主机（14,16,18,20和22）到具有重叠地址范围的多个寻址从端口（3和4）的访问。 在一种形式中，地址范围是相同的地址范围。 当所有寻址端口都忙时，交叉开关（12）使用共享从端口控制电路（48），配置寄存器（46）和从端口仲裁器逻辑（34,36,38,40,42和44）仲裁访问 。 确定新的访问请求是否比现有访问的优先级更高或更低。 基于对包括所请求的数据跳动的数量以及等待状态信息的各种因素的预测，首先将确定某个多个访问中的哪一个将首先完成，从而确定何时引导新的访问请求。 在一种模式中，动态地确定等待状态信息。