A write command is inputted from an outside, voltages of bit lines become VDL and VSS, and a voltage in accordance with a threshold voltage (LVT: low threshold voltage, MVT: mid threshold voltage, HVT: high threshold voltage) of a memory cell transistor is written into a storage node of a capacitor via the memory cell transistor. Thereafter, when a plate line connected to a plate side of the capacitor is driven from voltage VPL to voltage VPH and the voltage of the storage node is increased due to coupling, the voltage VDL of the bit line is reduced to the voltage VDP, and the voltage excessively written into the storage node is reduced in accordance with a level of a threshold voltage of the memory cell transistor, thereby reducing a variation in the voltage of the storage node due to a variation in the threshold voltage.