发明申请
- 专利标题: Semiconductor device and method of manufacturing thereof
- 专利标题(中): 半导体装置及其制造方法
-
申请号: US11329600申请日: 2006-01-10
-
公开(公告)号: US20060170112A1公开(公告)日: 2006-08-03
- 发明人: Naotaka Tanaka , Yasuhiro Yoshimura , Takahiro Naito , Takashi Akazawa
- 申请人: Naotaka Tanaka , Yasuhiro Yoshimura , Takahiro Naito , Takashi Akazawa
- 申请人地址: JP Tokyo
- 专利权人: Renesas Technology Corp.
- 当前专利权人: Renesas Technology Corp.
- 当前专利权人地址: JP Tokyo
- 优先权: JP2005-022478 20050131
- 主分类号: H01L23/52
- IPC分类号: H01L23/52
摘要:
A connection method for materializing a high-performance semiconductor system which is small-sized and high dense, is capable to three-dimensionally connecting a plurality of different kinds of semiconductor chips through piercing electrodes with shortest wiring lengths. The connection method enables high-speed operation with low noise, so as to obtain reliable and excellent connection in a short TAT at low costs. In a three-dimensional chip lamination composed of different kinds of semiconductor chips laminated one upon another with an interpose chip being interposed therebetween for connecting the upper and lower semiconductor chips, the semiconductor chips and the interposer chips are polished by grinding or the like at their rear surfaces so as to have thin thickness, holes are formed at rear surface positions corresponding to external electrode parts on the device side (front surface side) so that the holes extend to front surface electrodes, by dry etching or the like, and metal plating films are applied to the side walls of the holes and rear surface side, metal bumps of another semiconductor chip laminated at an upper stage being press-fitted into the holes applied with the metal plating films through deformation and being geometrically calked in the through holes formed in the semiconductor chip so as to electrically connected thereto.
公开/授权文献
- US07291929B2 Semiconductor device and method of manufacturing thereof 公开/授权日:2007-11-06
信息查询
IPC分类: