- 专利标题： Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
-
申请号： US11391170申请日： 2006-03-28
-
公开(公告)号： US20060176738A1公开(公告)日： 2006-08-10
- 发明人: Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
- 申请人： Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
- 主分类号： G11C16/04
- IPC分类号： G11C16/04
摘要：
A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.
信息查询
