公开(公告)号：US20240135993A1

公开(公告)日：2024-04-25

申请号：US18492625

申请日：2023-10-22

申请人： Fu-Chang Hsu

发明人： Fu-Chang Hsu

IPC分类号： G11C16/04 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

CPC分类号： G11C16/0483 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

摘要： Various 3D array structures and processes are disclosed. In an embodiment, a word line staircase structure is provided that includes a plurality of word line layers alternately deposited with a plurality of insulating layers to form a stack and a first word line stairstep that includes all the layers of the stack. The staircase structure also includes one or more additional word line stairsteps such that each successive additional word line stairstep is formed to include less layers of the stack than the preceding word line stairstep to form the word line staircase structure. The stairstep structure also includes multiple contact holes formed in each word line stairstep to contact multiple word line layers within that word line stairstep.

公开(公告)号：US20240130249A1

公开(公告)日：2024-04-18

申请号：US18365936

申请日：2023-08-04

申请人： Fu-Chang HSU ,  Kevin HSU

发明人： Fu-Chang HSU ,  Kevin HSU

IPC分类号： H10N60/10 ,  G06N10/00 ,  H03K3/38 ,  H10N69/00

CPC分类号： H10N60/11 ,  G06N10/00 ,  H03K3/38 ,  H10N60/128 ,  H10N69/00

摘要： A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel.

公开(公告)号：US20230154847A1

公开(公告)日：2023-05-18

申请号：US18055397

申请日：2022-11-14

申请人： Fu-Chang Hsu

发明人： Fu-Chang Hsu

IPC分类号： H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L21/683 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

CPC分类号： H01L23/5286 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/6835 ,  H01L21/8221 ,  H01L21/823871 ,  H01L29/66439 ,  H01L2221/68372

摘要： Advanced structures having MOSFET transistors and metal layers are disclosed. In one embodiment, a transistor structure is provided that includes a first transistor layer, a second transistor layer located under the first transistor layer, a first power bus layer located above the first transistor layer, a second power bus layer located under the second transistor layer, and a first interconnect layer located above the first power bus layer.

公开(公告)号：US20220037519A1

公开(公告)日：2022-02-03

申请号：US17389241

申请日：2021-07-29

申请人： Fu-Chang Hsu

发明人： Fu-Chang Hsu

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/06

摘要： Transistor structures and associated processes are disclosed. In an exemplary embodiment, a transistor structure is provided that includes a conductor layer divided into a plurality of separate conductor regions and a plurality of lateral transistors formed on top of the plurality of separate conductor regions, respectively. Each lateral transistor comprises a source, a drain, and a gate region, and at least one of the source, drain, and gate regions of each lateral transistor is conductively coupled underneath to its respective conductor region.

公开(公告)号：US20210296556A1

公开(公告)日：2021-09-23

申请号：US17209107

申请日：2021-03-22

申请人： Fu-Chang Hsu ,  Kevin Hsu

发明人： Fu-Chang Hsu ,  Kevin Hsu

IPC分类号： H01L39/22 ,  H01L27/18 ,  H03K3/38 ,  G06N10/00

摘要： A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel.

公开(公告)号：US20190108437A1

公开(公告)日：2019-04-11

申请号：US16006730

申请日：2018-06-12

申请人： Fu-Chang Hsu ,  Kevin Hsu

发明人： Fu-Chang Hsu ,  Kevin Hsu

IPC分类号： G06N3/063 ,  G06N3/04

摘要： Two and three-dimensional neural network arrays. In an exemplary embodiment, a two-dimensional (2D) neural network array includes a plurality of input neurons connected to a plurality of input lines, and a plurality of output neurons connected to a plurality of output lines. The 2D neural network array also includes synapse elements connected between the input lines and the output lines. Each synapse element includes a programmable resistive element. A three-dimensional (3D) neural network array includes a plurality of stacked two-dimensional (2D) neural network arrays each having a plurality of input neurons connected to a plurality of input layers and a plurality of output neurons connected to a plurality of output layers. The output layers intersect with the input layers and include synapse elements formed between intersecting regions of the input layers and the output layers. Each synapse element includes a programmable resistive element.

公开(公告)号：US20180165573A1

公开(公告)日：2018-06-14

申请号：US15835375

申请日：2017-12-07

申请人： Fu-Chang Hsu ,  Kevin Hsu

发明人： Fu-Chang Hsu ,  Kevin Hsu

IPC分类号： G06N3/063 ,  G06N3/04

CPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/0454

摘要： Three-dimensional neural network array. In an exemplary embodiment, a three-dimensional (3D) neural network includes a plurality of input conductors forming a plurality of stacked input layers having a first orientation, and at least one output conductor forming an output layer having the first orientation. The three-dimensional (3D) neural network also includes a plurality of hidden conductors having a second orientation. Each hidden conductor includes an in-line threshold element. The three-dimensional (3D) neural network also includes synapse elements coupled between the hidden conductors and the input conductors and between the hidden conductors and the output conductor. Each synapse element includes a programmable resistive element.

公开(公告)号：US20170148812A1

公开(公告)日：2017-05-25

申请号：US15355733

申请日：2016-11-18

申请人： Fu-Chang Hsu

发明人： Fu-Chang Hsu

IPC分类号： H01L27/115 ,  H01L21/768 ,  H01L21/306 ,  H01L23/528

CPC分类号： H01L27/11582 ,  H01L21/30604 ,  H01L21/743 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575

摘要： A 3D array inside a substrate trench. In one aspect, an apparatus includes a substrate, a trench region in the substrate that is defined by a trench wall, and a 3D array having stacked word line layers formed in the trench region that follow a contour of the trench wall. In one aspect, a method includes forming a trench region in a substrate that has a top surface, the trench region is defined by a trench wall, and forming a 3D array having stacked word line layers in the trench region so that the stacked word line layers follow a contour of the trench wall and have exposed ends substantially at a level of the top surface.

公开(公告)号：US09063849B2

公开(公告)日：2015-06-23

申请号：US13200141

申请日：2011-09-19

申请人： Peter Wung Lee ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Fu-Chang Hsu

IPC分类号： G06F12/00 ,  H05K3/00 ,  G06F12/06 ,  G06F12/02 ,  G11C5/06 ,  G11C7/10 ,  G11C11/00 ,  G11C16/32

CPC分类号： G06F12/0638 ,  G06F12/0246 ,  G06F2212/7208 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1045 ,  G11C11/005 ,  G11C16/32 ,  G11C2216/30 ,  Y02D10/13 ,  Y10T29/49124

摘要： A semiconductor chip contains four different memory types, EEPROM, NAND Flash, NOR Flash and SRAM, and a plurality of major serial/parallel interfaces such as I2C, SPI, SDI and SQI in one memory chip. The memory chip features write-while-write and read-while-write operations as well as read-while-transfer and write-while-transfer operations. The memory chip provides for eight pins of which two are for power and up to four pins have no connection for specific interfaces and uses a novel unified nonvolatile memory design that allow the integration together of the aforementioned memory types integrated together into the same semiconductor memory chip.

摘要翻译： 半导体芯片在一个存储器芯片中包含四种不同的存储器类型，EEPROM，NAND闪存，NOR闪存和SRAM以及多个主要的串行/并行接口，例如I2C，SPI，SDI和SQI。 内存芯片具有写时同时写入和读写操作以及读写同时传输和写时同时传输操作。 存储器芯片提供八个引脚，其中两个用于供电，最多四个引脚没有连接用于特定接口，并且使用新颖的统一的非易失性存储器设计，允许集成在一起的上述存储器类型集成在同一半导体存储器芯片 。

公开(公告)号：US08773903B2

公开(公告)日：2014-07-08

申请号：US13535681

申请日：2012-06-28

申请人： Peter Wung Lee ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Fu-Chang Hsu

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0425 ,  H01L27/11519 ,  H01L27/11521

摘要： A two transistor NOR flash memory cell has symmetrical source and drain structure manufactured by a NAND-based manufacturing process. The flash cell comprises a storage transistor made of a double-poly NMOS floating gate transistor and an access transistor made of a double-poly NMOS floating gate transistor, a poly1 NMOS transistor with poly1 and poly2 being shorted or a single-poly poly1 or poly2 NMOS transistor. The flash cell is programmed and erased by using a Fowler-Nordheim channel tunneling scheme. A NAND-based flash memory device includes an array of the flash cells arranged with parallel bit lines and source lines that are perpendicular to word lines. Write-row-decoder and read-row-decoder are designed for the flash memory device to provide appropriate voltages for the flash memory array in pre-program with verify, erase with verify, program and read operations in the unit of page, block, sector or chip.

摘要翻译： 双晶体管NOR闪存单元具有由基于NAND的制造工艺制造的对称的源极和漏极结构。 闪存单元包括由双多晶硅NMOS浮栅晶体管构成的存储晶体管和由双多晶硅NMOS浮栅晶体管构成的存取晶体管，poly1和poly2短路的poly1NMOS晶体管或单聚poly1或poly2 NMOS晶体管。 使用Fowler-Nordheim通道隧道方案对闪存单元进行编程和擦除。 基于NAND的闪速存储器件包括与并行位线排列的闪存单元的阵列和垂直于字线的源极线。 写行解码器和读行解码器专为闪存器件而设计，可在预编程中为闪速存储器阵列提供适当的电压，通过验证，擦除，以页面，块为单位进行验证，编程和读取操作， 部门或芯片。