Invention Application
- Patent Title: Delay locked loop circuitry for clock delay adjustment
- Patent Title (中): 延迟锁定环电路,用于时钟延迟调整
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Application No.: US11406557Application Date: 2006-04-18
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Publication No.: US20060188051A1Publication Date: 2006-08-24
- Inventor: Kevin Donnelly , Pak Chau , Mark Horowitz , Thomas Lee , Mark Johnson , Benedict Lau , Leung Yu , Bruno Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Tran , Donald Stark , Nhat Nguyen
- Applicant: Kevin Donnelly , Pak Chau , Mark Horowitz , Thomas Lee , Mark Johnson , Benedict Lau , Leung Yu , Bruno Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Tran , Donald Stark , Nhat Nguyen
- Main IPC: H04L7/00
- IPC: H04L7/00

Abstract:
A receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock includes first and second delay-locked loops. The first delay-locked loop is configured to generate a plurality of phase vectors from a first reference clock, and the second delay-locked loop is coupled to the first delay-locked loop and configured to generate the receive clock from at least one phase vector selected from the plurality of phase vectors and a second reference clock.
Public/Granted literature
- US07308065B2 Delay locked loop circuitry for clock delay adjustment Public/Granted day:2007-12-11
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