Invention Application
US20060188051A1 Delay locked loop circuitry for clock delay adjustment 失效
延迟锁定环电路,用于时钟延迟调整

Delay locked loop circuitry for clock delay adjustment
Abstract:
A receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock includes first and second delay-locked loops. The first delay-locked loop is configured to generate a plurality of phase vectors from a first reference clock, and the second delay-locked loop is coupled to the first delay-locked loop and configured to generate the receive clock from at least one phase vector selected from the plurality of phase vectors and a second reference clock.
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