公开(公告)号：US20060188051A1

公开(公告)日：2006-08-24

申请号：US11406557

申请日：2006-04-18

申请人： Kevin Donnelly ,  Pak Chau ,  Mark Horowitz ,  Thomas Lee ,  Mark Johnson ,  Benedict Lau ,  Leung Yu ,  Bruno Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Tran ,  Donald Stark ,  Nhat Nguyen

发明人： Kevin Donnelly ,  Pak Chau ,  Mark Horowitz ,  Thomas Lee ,  Mark Johnson ,  Benedict Lau ,  Leung Yu ,  Bruno Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Tran ,  Donald Stark ,  Nhat Nguyen

IPC分类号： H04L7/00

CPC分类号： H03K5/133 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/2481 ,  H03K2005/00026 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03K2005/00208 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0025 ,  H04L7/0037

摘要： A receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock includes first and second delay-locked loops. The first delay-locked loop is configured to generate a plurality of phase vectors from a first reference clock, and the second delay-locked loop is coupled to the first delay-locked loop and configured to generate the receive clock from at least one phase vector selected from the plurality of phase vectors and a second reference clock.

摘要翻译： 适于耦合到数据总线并被配置为根据接收时钟接收数据的接收机包括第一和第二延迟锁定环路。 第一延迟锁定环路被配置为从第一参考时钟产生多个相位矢量，并且第二延迟锁定环路耦合到第一延迟锁定环路并且被配置为从至少一个相位矢量生成接收时钟 从所述多个相位矢量中选择并具有第二参考时钟。

公开(公告)号：US20060120409A1

公开(公告)日：2006-06-08

申请号：US11327213

申请日：2006-01-05

申请人： Jared Zerbe ,  Kevin Donnelly ,  Stefanos Sidiropoulos ,  Donald Stark ,  Mark Horowitz ,  Leung Yu ,  Roxanne Vu ,  Jun Kim ,  Bruno Garlepp ,  Tsyr-Chyang Ho ,  Benedict Lau

发明人： Jared Zerbe ,  Kevin Donnelly ,  Stefanos Sidiropoulos ,  Donald Stark ,  Mark Horowitz ,  Leung Yu ,  Roxanne Vu ,  Jun Kim ,  Bruno Garlepp ,  Tsyr-Chyang Ho ,  Benedict Lau

IPC分类号： H04J3/06

CPC分类号： G06F13/364 ,  G06F1/10 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/404 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/7201 ,  G06F2212/7207 ,  G11C7/1045 ,  H04L7/0008 ,  H04L7/033

摘要： A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.

公开(公告)号：US20070083700A1

公开(公告)日：2007-04-12

申请号：US11609135

申请日：2006-12-11

申请人： Bruno Garlepp ,  Pak Chau ,  Kevin Donnelly ,  Clemenz Portmann ,  Donald Stark ,  Stefanos Sidiropoulos ,  Richard Barth ,  Paul Davis ,  Ely Tsern

发明人： Bruno Garlepp ,  Pak Chau ,  Kevin Donnelly ,  Clemenz Portmann ,  Donald Stark ,  Stefanos Sidiropoulos ,  Richard Barth ,  Paul Davis ,  Ely Tsern

IPC分类号： G06F13/28

CPC分类号： G11C7/1048 ,  G06F13/1689 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254

摘要： A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes means for tuning circuitry within the slave device such that the performance of the memory system is improved.

摘要翻译： 提供了一种用于调整存储器系统的性能的方法和装置。 存储器系统包括主设备和从设备。 存储器通道将主设备耦合到从设备，使得从设备经由存储器通道从主设备接收系统操作信息。 从设备还包括用于在从设备内调谐电路的装置，从而提高存储器系统的性能。

公开(公告)号：US20060059299A1

公开(公告)日：2006-03-16

申请号：US11270251

申请日：2005-11-08

申请人： Richard Barth ,  Ely Tsern ,  Mark Horowitz ,  Donald Stark ,  Craig Hampel ,  Frederick Ware ,  John Dillon ,  Nancy Dillon

发明人： Richard Barth ,  Ely Tsern ,  Mark Horowitz ,  Donald Stark ,  Craig Hampel ,  Frederick Ware ,  John Dillon ,  Nancy Dillon

IPC分类号： G06F12/00

CPC分类号： G11C7/1006 ,  G06F13/1615 ,  G11C7/10 ,  G11C7/1039 ,  G11C8/12 ,  G11C11/4076

摘要： A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.

公开(公告)号：US20070140035A1

公开(公告)日：2007-06-21

申请号：US11675054

申请日：2007-02-14

申请人： Richard Barth ,  Ely Tsern ,  Mark Horowitz ,  Donald Stark ,  Craig Hampel ,  Frederick Ware ,  John Dillon ,  Nancy Dillon

发明人： Richard Barth ,  Ely Tsern ,  Mark Horowitz ,  Donald Stark ,  Craig Hampel ,  Frederick Ware ,  John Dillon ,  Nancy Dillon

IPC分类号： G11C8/00

CPC分类号： G11C7/1006 ,  G06F13/1615 ,  G11C7/10 ,  G11C7/1039 ,  G11C8/12 ,  G11C11/4076

摘要： A semiconductor memory device has a memory core that includes at least eight banks of dynamic random access storage cells and an internal data bus coupled to the memory core. The internal data bus receives a plurality of data bits from a selected bank of the memory core. The semiconductor memory device further comprises a first interface to receive a read command from external to the semiconductor memory device and a second interface to output first and second subsets of the plurality of data bits. The first subset is output during a first phase of an external clock signal and the second subset is output during a second phase of the external clock signal. The first phase includes a first edge transition and the second phase includes a second edge transition. The second edge transition is an opposite edge transition with respect to the first edge transition.

摘要翻译： 半导体存储器件具有包括至少八个动态随机存取存储单元组和耦合到存储器核的内部数据总线的存储器核心。 内部数据总线从存储器核心的选定组接收多个数据位。 半导体存储器件还包括从外部接收半导体存储器件的读取命令的第一接口和用于输出多个数据位的第一和第二子集的第二接口。 在外部时钟信号的第一阶段期间输出第一子集，并且在外部时钟信号的第二阶段期间输出第二子集。 第一阶段包括第一边缘转变，第二阶段包括第二边缘过渡。 第二边缘转变是相对于第一边缘转变的相反边缘转变。

公开(公告)号：US20050237094A1

公开(公告)日：2005-10-27

申请号：US11148783

申请日：2005-06-08

申请人： Donald Stark ,  Jun Kim ,  Kurt Knorpp ,  Michael Ching ,  Natsuki Kushiyama

发明人： Donald Stark ,  Jun Kim ,  Kurt Knorpp ,  Michael Ching ,  Natsuki Kushiyama

IPC分类号： G11C7/10 ,  H03B1/00 ,  H03K17/16 ,  H03K19/003

CPC分类号： H03K17/164 ,  G11C7/1051 ,  H03K19/00384

摘要： An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current 5 river receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.

摘要翻译： 输出驱动器具有输出多路复用器和输出电流驱动器。 输出多路复用器接收数据信号并输出​​q-节点信号。 输出电流5河接收q节点信号，并根据q-节点信号驱动总线。 输出多路复用器以各种方式处理数据信号以产生q-结点信号。 输出电流驱动器响应于当前控制位以选择输出驱动电流的量。 此外，控制输出多路复用器，使得输出电流驱动器的输出阻抗保持在预定范围内。

公开(公告)号：US20050220235A1

公开(公告)日：2005-10-06

申请号：US11130506

申请日：2005-05-16

申请人： Donald Stark ,  Jun Kim ,  Stefanos Sidiropoulos

发明人： Donald Stark ,  Jun Kim ,  Stefanos Sidiropoulos

IPC分类号： H04J3/06 ,  H04L7/00 ,  H04L7/02

CPC分类号： H04L7/0008 ,  G06F13/4072 ,  G11C7/1003 ,  G11C7/222 ,  H04L7/02

摘要： A system includes a master device connected to one or more slave devices via a channel, the channel communicating an externally generated first system clock towards the master device. A delay locked loop circuit receives the first system clock and a second phase feedback signal as inputs and generates a transmit clock signal. A phase offset circuit receives the transmit system clock and generates a phase shifted version of the transmit clock signal as a second system clock. A first phase detector receives a receive system clock and the transmit system clock and generates a first phase feedback signal. A delay element receives the first system clock and the first phase feedback signal and generates a delayed first system clock. A second phase detector receives the delayed first system clock and the second system clock and generates the second phase feedback signal.

摘要翻译： 系统包括经由信道连接到一个或多个从设备的主设备，该信道将外部产生的第一系统时钟传送到主设备。 延迟锁定环电路接收第一系统时钟和第二相位反馈信号作为输入，并产生发送时钟信号。 相位偏移电路接收发射系统时钟并产生作为第二系统时钟的发送时钟信号的相移版本。 第一相位检测器接收接收系统时钟和发射系统时钟并产生第一相位反馈信号。 延迟元件接收第一系统时钟和第一相位反馈信号并产生延迟的第一系统时钟。 第二相位检测器接收延迟的第一系统时钟和第二系统时钟并产生第二相位反馈信号。

公开(公告)号：US20070242532A1

公开(公告)日：2007-10-18

申请号：US11692159

申请日：2007-03-27

申请人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarro ,  David Nguyen

发明人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarro ,  David Nguyen

IPC分类号： G11C7/10 ,  G06F13/00

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： An integrated circuit memory device includes a first set of pins and a memory core. The first set of pins receive, using a clock signal, a write command and a read command. Control information is issued internally in response to the write command after a predetermined delay time transpires following receipt of the write command, the control information initiating the write operation in the memory device. A second set of pins output the read data after a first delay time transpires from when the read command is received. Each pin of the second set of pins outputs two bits of read data during a clock cycle of the clock signal. The second set of pins also receive write data after a second delay time has transpired from when the write command is received. The second delay time is based on the first delay time.

摘要翻译： 集成电路存储器件包括第一组引脚和存储器核。 第一组引脚使用时钟信号接收写入命令和读取命令。 控制信息在接收到写入命令之后经过预定的延迟时间之后响应写入命令被发出，控制信息在存储器件中启动写入操作。 第二组引脚在从接收到读命令之后发生第一延迟时间后输出读数据。 第二组引脚的每个引脚在时钟信号的时钟周期期间输出两位读取数据。 第二组引脚还在接收到写入命令之后延迟了第二个延迟时间之后也接收到写入数据。 第二延迟时间基于第一延迟时间。

公开(公告)号：US20070159912A1

公开(公告)日：2007-07-12

申请号：US11681384

申请日：2007-03-02

申请人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarro ,  David Nguyen

发明人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarro ,  David Nguyen

IPC分类号： G06F13/28 ,  G11C8/00 ,  G11C7/00 ,  G06F12/00

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： An integrated circuit memory device having delayed write command processing includes a first set of pins coupled to a memory core, the first set of pins to receive a row address followed by a column address. A second set of pins, coupled to memory core, are used to receive a sense command followed by a write command. The sense command specifies the sensing of a row of memory cells identified by the row address, and the write command specifies that the memory device receive write data and store the write data at a column location identified by the column address. The write command is posted internally to the memory device after a first delay has transpired from when the write command is received at the second set of pins.

摘要翻译： 具有延迟写入命令处理的集成电路存储器件包括耦合到存储器核心的第一组引脚，第一组引脚以接收列地址的行地址。 耦合到存储器核心的第二组引脚用于接收感测命令，后接写入命令。 感测命令指定感测由行地址识别的一行存储器单元，并且写入命令指定存储器件接收写入数据并将写入数据存储在由列地址标识的列位置处。 在从第二组引脚接收到写命令之后第一个延迟发生之后，写入命令在内部发布到存储器件中。

公开(公告)号：US20050268196A1

公开(公告)日：2005-12-01

申请号：US11201609

申请日：2005-08-10

申请人： Timothy Chang ,  Donald Stark

发明人： Timothy Chang ,  Donald Stark

IPC分类号： G01R31/319 ,  G01R31/3193 ,  G01R31/28 ,  G06F11/00

CPC分类号： G01R31/31919 ,  G01R31/31935

摘要： An efficient method and apparatus for characterizing circuit devices is disclosed. In one embodiment, multiple test patterns for testing a circuit device are stored in a tester. Each test pattern includes both test data and control data that defines at least in part a sweep point at which the circuit device is tested. Thus, the tester can generate stimulus vectors for multiple sweep points without requiring control system intervention. Pass/fail indicators, each of which represents pass/fail results associated with a sweep point, are derived from the test results and stored in a Fail Capture Memory. A pass/fail boundary of the DUT can be determined from the contents of the Fail Capture Memory.

摘要翻译： 公开了一种用于表征电路装置的有效方法和装置。 在一个实施例中，用于测试电路设备的多个测试图案被存储在测试器中。 每个测试模式包括测试数据和至少部分地定义电路设备被测试的扫描点的控制数据。 因此，测试者可以产生多个扫描点的刺激向量，而不需要控制系统干预。 通过/失败指示器，每个都表示与扫描点相关联的通过/失败结果，从测试结果中导出并存储在故障捕获内存中。 DUT的通过/失败边界可以根据故障捕获存储器的内容来确定。