发明申请
- 专利标题: Semiconductor device having optimized shallow junction geometries and method for fabrication thereof
- 专利标题(中): 具有优化的浅结几何形状的半导体器件及其制造方法
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申请号: US11064583申请日: 2005-02-24
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公开(公告)号: US20060189066A1公开(公告)日: 2006-08-24
- 发明人: Brian Hornung , Jong Yoon , Deborah Riley , Amitava Chatterjee
- 申请人: Brian Hornung , Jong Yoon , Deborah Riley , Amitava Chatterjee
- 申请人地址: US TX Dallas
- 专利权人: Texas Instruments, Incorporated
- 当前专利权人: Texas Instruments, Incorporated
- 当前专利权人地址: US TX Dallas
- 主分类号: H01L21/8238
- IPC分类号: H01L21/8238
摘要:
The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). In one embodiment, the method includes growing an oxide layer 120 from a substrate 104, 106 over a first dopant region 122 and a second dopant region 128, implanting a first dopant through the oxide layer 120, into the substrate 104 in the first dopant region 122, and adjacent a gate structure 114, and substantially removing the oxide layer 120 from the substrate within the second dopant region 128. Subsequent to the removal of the oxide layer 120 in the second dopant region 128, a second dopant that is opposite in type to the first dopant is implanted into the substrate 106 and within the second dopant region 128 and adjacent a gate structure 114.
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