公开(公告)号：US20060292885A1

公开(公告)日：2006-12-28

申请号：US11165232

申请日：2005-06-24

申请人： Vladimir Ukraintsev ,  Mark Mason ,  James Blatchford ,  Brian Smith ,  Brian Hornung ,  Dirk Anderson

发明人： Vladimir Ukraintsev ,  Mark Mason ,  James Blatchford ,  Brian Smith ,  Brian Hornung ,  Dirk Anderson

IPC分类号： H01L23/58 ,  H01L21/302

CPC分类号： G03F7/70425 ,  H01L21/0273

摘要： A semiconductor device and a method for fabricating a semiconductor device with reduced line bending is provided. The method can include forming a first layer and depositing a photoresist layer on the first layer. The photoresist layer can be patterned, such that the patterning comprises at least one support feature disposed adjacent to an outside of a corner feature.

摘要翻译： 提供一种半导体器件和用于制造具有减少的线弯曲的半导体器件的方法。 该方法可以包括形成第一层并在第一层上沉积光致抗蚀剂层。 光致抗蚀剂层可以被图案化，使得图案化包括邻近拐角特征的外部设置的至少一个支撑特征。

公开(公告)号：US20050059260A1

公开(公告)日：2005-03-17

申请号：US10810905

申请日：2004-03-26

申请人： Haowen Bu ,  Brian Hornung ,  P.R. Chidambaram ,  Amitabh Jain ,  Rajesh Khamankar ,  Nandu Mahalingam ,  Srinivansan Chakravarthi

发明人： Haowen Bu ,  Brian Hornung ,  P.R. Chidambaram ,  Amitabh Jain ,  Rajesh Khamankar ,  Nandu Mahalingam ,  Srinivansan Chakravarthi

IPC分类号： H01L21/00 ,  H01L21/265 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/08 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L21/26506 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/3185 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845

摘要： The present invention teaches the formation of CMOS transistors using interfacial nitrogen at the interface between the lightly doped extension regions and an overlying insulating layer in combination with a capping layer of silicon nitride, both prior to the final source/drain anneal. Doses and energies may be increased for the P-channel lightly-doped drain, source and drain regions. The resulting transistors exhibit desirably high drive current and low off-state leakage current and overlap capacitance.

摘要翻译： 本发明教导了在最终的源极/漏极退火之前，在轻掺杂的延伸区域之间的界面处的界面氮和与氮化硅覆盖层结合的上覆绝缘层的CMOS晶体管的形成。 P沟道轻掺杂漏极，源极和漏极区域的剂量和能量可能会增加。 所得到的晶体管显示期望的高驱动电流和低截止状态的漏电流和重叠电容。

公开(公告)号：US20060001105A1

公开(公告)日：2006-01-05

申请号：US11179210

申请日：2005-07-12

申请人： Brian Hornung ,  Xin Zhang ,  Lance Robertson ,  Srinivasan Chakravarthi ,  P. Chidambaram

发明人： Brian Hornung ,  Xin Zhang ,  Lance Robertson ,  Srinivasan Chakravarthi ,  P. Chidambaram

IPC分类号： H01L29/76

CPC分类号： H01L21/823814 ,  H01L21/823864

摘要： The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises growing an oxide layer (120) on a gate structure (114) and a substrate (102) and implanting a dopant (124) into the substrate (102) and the oxide layer (120). Implantation is such that a portion of the dopant (124) remains in the oxide layer (120) to form an implanted oxide layer (126). The method further includes depositing a protective oxide layer (132) on the implanted oxide layer (126) and forming etch-resistant off-set spacers (134). The etch-resistant off-set spacers (134) are formed adjacent sidewalls of the gate structure (114) and on the protective oxide layer (132). The etch resistant off-set spacers having an inner perimeter (135) adjacent the sidewalls and an opposing outer perimeter (136). The method also comprises removing portions of the protective oxide layer (132) lying outside the outer perimeter (136) of the etch-resistant off-set spacers (134). Other embodiments of the present invention include a transistor device (200) and method of manufacturing an integrated circuit (300).

公开(公告)号：US20060189066A1

公开(公告)日：2006-08-24

申请号：US11064583

申请日：2005-02-24

申请人： Brian Hornung ,  Jong Yoon ,  Deborah Riley ,  Amitava Chatterjee

发明人： Brian Hornung ,  Jong Yoon ,  Deborah Riley ,  Amitava Chatterjee

IPC分类号： H01L21/8238

CPC分类号： H01L21/823864 ,  H01L21/823814

摘要： The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). In one embodiment, the method includes growing an oxide layer 120 from a substrate 104, 106 over a first dopant region 122 and a second dopant region 128, implanting a first dopant through the oxide layer 120, into the substrate 104 in the first dopant region 122, and adjacent a gate structure 114, and substantially removing the oxide layer 120 from the substrate within the second dopant region 128. Subsequent to the removal of the oxide layer 120 in the second dopant region 128, a second dopant that is opposite in type to the first dopant is implanted into the substrate 106 and within the second dopant region 128 and adjacent a gate structure 114.

摘要翻译： 本发明在一个实施例中提供一种制造半导体器件（100）的方法。 在一个实施例中，该方法包括在第一掺杂剂区域122和第二掺杂剂区域128之上从衬底104,106生长氧化物层120，将第一掺杂剂注入到氧化物层120中，将第一掺杂剂注入第一掺杂剂区域 122，并且与栅极结构114相邻，并且在第二掺杂区128内基本上从衬底去除氧化物层120.在第二掺杂区128中去除氧化物层120之后，与第二掺杂区128相反的第二掺杂剂 第一掺杂剂注入到衬底106中并且在第二掺杂剂区128内并且与栅极结构114相邻。

公开(公告)号：US20060154411A1

公开(公告)日：2006-07-13

申请号：US11372430

申请日：2006-03-09

申请人： Haowen Bu ,  Brian Hornung ,  P.R. Chidambaram ,  Amitabh Jain ,  Rajesh Khamankar ,  Nandu Mahalingam ,  Srinivansan Chakravarthi

发明人： Haowen Bu ,  Brian Hornung ,  P.R. Chidambaram ,  Amitabh Jain ,  Rajesh Khamankar ,  Nandu Mahalingam ,  Srinivansan Chakravarthi

IPC分类号： H01L21/338 ,  H01L21/31

CPC分类号： H01L21/26506 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/3185 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845

摘要： The present invention teaches the formation of CMOS transistors using interfacial nitrogen at the interface between the lightly doped extension regions and an overlying insulating layer in combination with a capping layer of silicon nitride, both prior to the final source/drain anneal. Doses and energies may be increased for the P-channel lightly-doped drain, source and drain regions. The resulting transistors exhibit desirably high drive current and low off-state leakage current and overlap capacitance.

摘要翻译： 本发明教导了在最终的源极/漏极退火之前，在轻掺杂的延伸区域之间的界面处的界面氮和与氮化硅覆盖层结合的上覆绝缘层的CMOS晶体管的形成。 P沟道轻掺杂漏极，源极和漏极区域的剂量和能量可能会增加。 所得到的晶体管显示期望的高驱动电流和低截止状态的漏电流和重叠电容。

公开(公告)号：US20050245021A1

公开(公告)日：2005-11-03

申请号：US10835121

申请日：2004-04-29

申请人： Brian Hornung ,  Xin Zhang ,  Lance Robertson ,  Srinivasan Chakravarthi ,  P.R. Chidambaram

发明人： Brian Hornung ,  Xin Zhang ,  Lance Robertson ,  Srinivasan Chakravarthi ,  P.R. Chidambaram

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/823864

摘要： The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises growing an oxide layer (120) on a gate structure (114) and a substrate (102) and implanting a dopant (124) into the substrate (102) and the oxide layer (120). Implantation is such that a portion of the dopant (124) remains in the oxide layer (120) to form an implanted oxide layer (126). The method further includes depositing a protective oxide layer (132) on the implanted oxide layer (126) and forming etch-resistant off-set spacers (134). The etch-resistant off-set spacers (134) are formed adjacent sidewalls of the gate structure (114) and on the protective oxide layer (132). The etch resistant off-set spacers having an inner perimeter (135) adjacent the sidewalls and an opposing outer perimeter (136). The method also comprises removing portions of the protective oxide layer (132) lying outside the outer perimeter (136) of the etch-resistant off-set spacers (134). Other embodiments of the present invention include a transistor device (200) and method of manufacturing an integrated circuit (300).

摘要翻译： 本发明在一个实施例中提供一种制造半导体器件（100）的方法。 该方法包括在栅极结构（114）和衬底（102）上生长氧化物层（120）并将掺杂剂（124）注入到衬底（102）和氧化物层（120）中。 注入使得掺杂剂（124）的一部分保留在氧化物层（120）中以形成注入的氧化物层（126）。 该方法还包括在注入的氧化物层（126）上沉积保护性氧化物层（132）并且形成耐腐蚀的偏置间隔物（134）。 在栅极结构（114）的侧壁和保护氧化物层（132）上形成耐蚀刻偏置间隔物（134）。 耐腐蚀的偏置间隔件具有邻近侧壁的内周边（135）和相对的外周边（136）。 该方法还包括去除位于耐蚀刻偏移间隔物（134）的外周（136）外的保护氧化物层（132）的部分。 本发明的其他实施例包括晶体管器件（200）和制造集成电路（300）的方法。