发明申请
US20060190874A1 Method and system for formal unidirectional bus verification 有权
正式单向总线验证方法与系统

Method and system for formal unidirectional bus verification
摘要:
A method, system and computer program product for performing verification is disclosed. A high-level description of a design is created and constrained drivers are synthesized from the high-level description of the design. A testbench is generated from the high-level description of the design and the constrained drivers and a formal equivalence is evaluated on the testbench to perform verification.
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