发明申请
- 专利标题： Method for integrally checking chip and package substrate layouts for errors
- 专利标题（中）： 整体检查芯片和封装衬底布局的错误方法
-
申请号： US11089108申请日： 2005-03-24
-
公开(公告)号： US20060217916A1公开(公告)日： 2006-09-28
- 发明人: Chia-Lin Cheng , E. Wu , Shih-Cherng Chang , Kuo-Yin Chen
- 申请人： Chia-Lin Cheng , E. Wu , Shih-Cherng Chang , Kuo-Yin Chen
- 专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 主分类号： G01R27/28
- IPC分类号： G01R27/28
摘要：
A method and system for integrally checking a chip layout dataset and a package substrate layout dataset for errors are disclosed. The package substrate layout dataset is converted from a first format into a second format in which the chip layout dataset is provided. The chip layout dataset of the second format is combined with the package substrate layout dataset of the second format into a combined dataset. The combined dataset is then checked for errors or design rule violations.
公开/授权文献
信息查询
