发明申请
US20060226493A1 High performance PFET header in hybrid orientation technology for leakage reduction in digital CMOS VLSI designs
失效
用于混合定向技术的高性能PFET接头，用于数字CMOS VLSI设计中的漏电减少
- 专利标题： High performance PFET header in hybrid orientation technology for leakage reduction in digital CMOS VLSI designs
- 专利标题（中）： 用于混合定向技术的高性能PFET接头，用于数字CMOS VLSI设计中的漏电减少
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申请号： US11100883申请日： 2005-04-07
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公开(公告)号： US20060226493A1公开(公告)日： 2006-10-12
- 发明人: Ching-Te Chuang , Koushik Das , Shih-Hsien Lo
- 申请人： Ching-Te Chuang , Koushik Das , Shih-Hsien Lo
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 主分类号： H01L29/94
- IPC分类号： H01L29/94
摘要：
Discloses are CMOS circuit designs that combine MTCMOS and hybrid orientation technology to achieve the dual objectives of high performance and low standby leakage power. The invention utilizes novel combinations of a thick-oxide high-VTH PFET header with various gate- and body-biased schemes in HOT technology to significantly reduce the performance penalty associated with conventional PFET headers. A first embodiment of the invention provides a HOT-B high-VTH thick oxide bulk PFET header scheme. This header scheme can be expanded by application of a positive gate bias VPOS (VPOS>VDD) to the HOT-B PFET header during standby mode and a negative gate bias VNEG (VNEG