- 专利标题: Fractional-N baseband frequency synthesizer in bluetooth applications
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申请号: US11109701申请日: 2005-04-20
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公开(公告)号: US20060238226A1公开(公告)日: 2006-10-26
- 发明人: William Holland , Wenzhe Luo , Zhigang Ma , Dale Nelson , Harold Simmonds , Lizhong Sun , Xiangqun Sun
- 申请人: William Holland , Wenzhe Luo , Zhigang Ma , Dale Nelson , Harold Simmonds , Lizhong Sun , Xiangqun Sun
- 主分类号: H03K23/00
- IPC分类号: H03K23/00
摘要:
A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock signal, e.g., 12.00, 12.80, 13.00, 15.36, 16.80, 19.20, 19.44, 19.68, 19.80, and 26.00 MHz. A fractional-N frequency divider is implemented with a PLL including a variable divider allowing the use of virtually any reference frequency input to generate a locked 156 MHz clock signal used as a basis for a 12 MHz or 13 MHz baseband clock signal. A residue feedback sigma-delta modulator provides a varying integer sequence to an integer divider in a feedback path of the PLL, effectively allowing division by non-integer numbers in the PLL. Thus, the PLL can be referenced to virtually any reference clock and still provide a fixed output clock signal (e.g., 12 or 13 MHz).
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