公开(公告)号：US20060291545A1

公开(公告)日：2006-12-28

申请号：US11206314

申请日：2005-08-17

Applicant: King-Hon Lau ,  Johannes Ransijn ,  Harold Simmonds ,  James Yoder

Inventor： King-Hon Lau ,  Johannes Ransijn ,  Harold Simmonds ,  James Yoder

IPC: H04L5/16

CPC classification number: H04M3/005 ,  H04L5/1423 ,  H04L25/0266

Abstract: The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the ΣΔ rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.

Abstract translation: 本发明提供一种通信协议和串行接口，其具有近似固定的接口时钟并且能够适应各种通信速率。 接口采用可扩展或缩小的可变长度帧，以获得所需的通信速率，即使接口时钟速率保持近似恒定。 本发明还提供了一种用于设计敏捷屏障界面的方法。 特别地，屏障时钟速率优选地被选择为屏障接口必须处理的各种通信速率的近似公倍数。 然后可以通过将屏障时钟速率除以SigmaDelta速率来获得对应于每个通信速率的帧长度。 最后，本发明提供了能够以各种数据速率和大致固定的接口时钟速率通过串行接口传送数据的敏捷障碍。

公开(公告)号：US20060238226A1

公开(公告)日：2006-10-26

申请号：US11109701

申请日：2005-04-20

Applicant: William Holland ,  Wenzhe Luo ,  Zhigang Ma ,  Dale Nelson ,  Harold Simmonds ,  Lizhong Sun ,  Xiangqun Sun

Inventor： William Holland ,  Wenzhe Luo ,  Zhigang Ma ,  Dale Nelson ,  Harold Simmonds ,  Lizhong Sun ,  Xiangqun Sun

IPC: H03K23/00

CPC classification number: G06F7/68 ,  H03L7/1976

Abstract: A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock signal, e.g., 12.00, 12.80, 13.00, 15.36, 16.80, 19.20, 19.44, 19.68, 19.80, and 26.00 MHz. A fractional-N frequency divider is implemented with a PLL including a variable divider allowing the use of virtually any reference frequency input to generate a locked 156 MHz clock signal used as a basis for a 12 MHz or 13 MHz baseband clock signal. A residue feedback sigma-delta modulator provides a varying integer sequence to an integer divider in a feedback path of the PLL, effectively allowing division by non-integer numbers in the PLL. Thus, the PLL can be referenced to virtually any reference clock and still provide a fixed output clock signal (e.g., 12 or 13 MHz).

公开(公告)号：US1272922A

公开(公告)日：1918-07-16

申请号：US19672017

申请日：1917-10-15

Applicant: DAVIS HAROLD SIMMONDS ,  DAVIS MARY DAVIDSON

Inventor： DAVIS HAROLD SIMMONDS ,  DAVIS MARY DAVIDSON

CPC classification number: G01N7/10