• 专利标题: Semiconductor device with shallow trench isolation and its manufacture method
  • 申请号: US11429962
    申请日: 2006-05-09
  • 公开(公告)号: US20060255426A1
    公开(公告)日: 2006-11-16
  • 发明人: Kengo InoueHiroyuki Ota
  • 申请人: Kengo InoueHiroyuki Ota
  • 申请人地址: JP Kawasaki 211-8588
  • 专利权人: FUJITSU LIMITED
  • 当前专利权人: FUJITSU LIMITED
  • 当前专利权人地址: JP Kawasaki 211-8588
  • 优先权: JP2004-060210 20040304
  • 主分类号: H01L29/00
  • IPC分类号: H01L29/00
Semiconductor device with shallow trench isolation and its manufacture method
摘要:
A semiconductor device manufacturing method includes the steps of: (a) forming a stopper layer for chemical mechanical polishing on a surface of a semiconductor substrate; (b) forming an element isolation trench in the stopper layer and the semiconductor substrate; (c) depositing a nitride film covering an inner surface of the trench; (d) depositing a first oxide film through high density plasma CVD, the first oxide film burying at least a lower portion of the trench deposited with the nitride film; (e) washing out the first oxide film on a side wall of the trench by dilute hydrofluoric acid; (f) depositing a second oxide film by high density plasma CVD, the second oxide film burying the trench after the washing-out; and (g) removing the oxide films on the stopper layer by chemical mechanical polishing.
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