发明申请
US20060265162A1 Aggregated run-to-run process control for wafer yield optimization
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用于晶圆产量优化的聚合运行过程控制
- 专利标题: Aggregated run-to-run process control for wafer yield optimization
- 专利标题(中): 用于晶圆产量优化的聚合运行过程控制
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申请号: US11123609申请日: 2005-05-04
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公开(公告)号: US20060265162A1公开(公告)日: 2006-11-23
- 发明人: Amelia Muro , Andrew Walker , Yeak-Chong Wong
- 申请人: Amelia Muro , Andrew Walker , Yeak-Chong Wong
- 专利权人: HITACHI GLOBAL STORAGE TECHNOLOGIES
- 当前专利权人: HITACHI GLOBAL STORAGE TECHNOLOGIES
- 主分类号: G01N37/00
- IPC分类号: G01N37/00 ; G06F19/00
摘要:
A method for processing wafers in a batch processing tool that optimizes yield by minimizing within batch wafer variation in a wafer process. In a tool having a plurality of available wafer positions for a batch process, the method is useful when less than a full batch of wafers is to be processed. All of the possible wafer position combinations are determined and the within batch variation for each position combination is determined. The wafer position combination resulting in the least amount of within batch variation in the wafer process is then selected as the wafer placement combination for use in the process.
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