- 专利标题: Method of manufacturing semiconductor integrated circuit device, and semiconductor integrated circuit device made by its method
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申请号: US11503161申请日: 2006-08-14
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公开(公告)号: US20060275969A1公开(公告)日: 2006-12-07
- 发明人: Satoshi Sakai , Daichi Matsumoto , Katsuyuki Asaka , Masatoshi Hasegawa , Kazutaka Mori
- 申请人: Satoshi Sakai , Daichi Matsumoto , Katsuyuki Asaka , Masatoshi Hasegawa , Kazutaka Mori
- 专利权人: Renesas Technology Corp.
- 当前专利权人: Renesas Technology Corp.
- 优先权: JP2003-157737 20030603
- 主分类号: H01L21/8234
- IPC分类号: H01L21/8234
摘要:
Mutual diffusion of impurities in a gate electrode is suppressed near a boundary between an n-channel type MISFET and a p-channel type MISFET, which adopt a polycide's dual-gate structure. Since a gate electrode of an n-channel type MISFET and a gate electrode of a p-channel type MISFET are of mutually different conductivity types, they are separated to prevent the mutual diffusion of the impurities and are electrically connected to each other via a metallic wiring formed in the following steps. In a step before a gate electrode material is patterned to separate the gate electrodes, the mutual diffusion of the impurities before forming the gate electrodes is prevented by performing no heat treatment at a temperature of 700° C. or higher.
公开/授权文献
- US3047185A Receptacle apparatus 公开/授权日:1962-07-31