A memory system and method is disclosed. In one embodiment, the memory system includes a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connecting lines are arranged in a respectively specified topology. The connecting lines include first connecting lines forming transfer channels for a protocol based transfer of data and command signal streams from the memory controller to at least one of the memory chips on the memory module and from there to the memory controller, respectively. Second connecting lines are routed separately from the memory controller directly to at least one of the memory chips on the memory module for transferring select information to the at least one memory chip separately from the data and command signal streams.