发明申请
- 专利标题： Method of reducing warpage in an over-molded IC package
- 专利标题（中）： 减少翘曲成型IC封装的方法
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申请号： US11171095申请日： 2005-06-30
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公开(公告)号： US20070004094A1公开(公告)日： 2007-01-04
- 发明人: Hem Takiar , Shrikar Bhagath , Ken Wang
- 申请人： Hem Takiar , Shrikar Bhagath , Ken Wang
- 主分类号： H01L21/58
- IPC分类号： H01L21/58
摘要：
A dummy circuit pattern is disclosed on a surface of a substrate for a semiconductor package, the dummy circuit pattern including straight line segments having a length controlled so as not to generate stresses within the line segments above a desired stress. The dummy circuit pattern may be formed of lines, or contiguous or spaced polygons, such as hexagons. Portions of the dummy circuit pattern may also be formed with an orientation, size and position that are randomly selected.
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