An object of the present invention is to provide, in an FeRAM memory device fixed to a cell plate, a memory device in which RES_N (source line) of a reset transistor for resetting a storage node has a low resistance. A memory cell (101) includes a ferroelectric capacitance, a first MOS transistor for selecting the memory cell, and a second MOS transistor which is a reset transistor for resetting the storage node. Potential is supplied to RES_N (source line) (impurity activation region) of the second MOS transistor through the following two conductive layers: an impurity activation region which is a conductive layer below an upper electrode of the ferroelectric capacitance, and a bit-line formation wiring layer making up a bit line BL. This configuration makes it possible to supply potential to RES_N (source line) with a low resistance and perform a stable operation.