公开(公告)号：US08446751B2

公开(公告)日：2013-05-21

申请号：US13170645

申请日：2011-06-28

申请人： Yasuo Murakuki ,  Shunichi Iwanari ,  Yoshiaki Nakao

发明人： Yasuo Murakuki ,  Shunichi Iwanari ,  Yoshiaki Nakao

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C5/10 ,  G11C7/02 ,  G11C11/22 ,  G11C11/24

CPC分类号： H01L27/105 ,  H01L27/0207 ,  H01L27/11509 ,  H01L28/55

摘要： The demand for reducing the size and increasing the degree of integration of semiconductor memory devices has increased. In a semiconductor memory device, a smoothing capacitor which has to be provided therein for stabilizing a power supply voltage etc. is formed in an underlying layer of memory cells A and B to overlap the two memory cells A and B which are adjacent each other. Thus, an area occupied by the smoothing capacitor having a large capacity can be reduced to increase the degree of integration, and the smoothing capacitor having a large capacity can be provided in the semiconductor memory device.

摘要翻译： 减小半导体存储器件的尺寸和集成程度的需求增加。 在半导体存储器件中，必须在其中提供用于稳定电源电压等的平滑电容器形成在存储单元A和B的下层中以与彼此相邻的两个存储单元A和B重叠。 因此，能够减小由容量大的平滑电容器占有的面积，提高积分度，能够在半导体存储装置中设置容量大的平滑电容器。

公开(公告)号：US07485935B2

公开(公告)日：2009-02-03

申请号：US11790009

申请日：2007-04-23

申请人： Takashi Miki ,  Yasuo Murakuki

发明人： Takashi Miki ,  Yasuo Murakuki

IPC分类号： H01L27/088

CPC分类号： G11C11/22

摘要： A semiconductor memory device is provided with plural memory cells, plural bit lines BL, each bit line being commonly connected to the plural memory cells that are arranged in the same row, plural word lines WL and plural plate lines CP, each word line and each plate line being commonly connected to the plural memory cells that are arranged in the same column, plural plate voltage supply lines CPS arranged in the column direction, and means for electrically connecting each of the plural plate voltage supply lines to each of the corresponding plural plate lines. The plate voltage supply lines are composed of a material having a resistance lower than that of the plate lines, each of capacitors of the plural memory cells is covered with a hydrogen barrier film HB at its periphery, the plural plate voltage supply lines are disposed beneath the hydrogen barrier film HB, and the plural plate voltage supply lines CPS are, when viewed in a plane, electrically connected to the same plate line at plural positions of the same plate line, within a region where the hydrogen barrier film is disposed.

摘要翻译： 半导体存储器件具有多个存储单元，多个位线BL，每个位线共同连接到排列在同一行的多个存储单元，多个字线WL和多个板条CP，每个字线和每个 板线通常连接到布置在同一列中的多个存储单元，沿列方向排列的多个板电压供给线CPS，以及用于将多个板电压供给线中的每一个电连接到相应的多个板中的每一个的装置 线条。 板电压供给线由具有低于板线电阻的材料构成，多个存储单元的每个电容器在其周边被氢阻挡膜HB覆盖，多个板电压供给线设置在 在与设置有氢阻挡膜的区域相同的板线的多个位置上的同一板线电连接的情况下，氢阻挡膜HB和多个板电压供给线CPS为同一平面。

公开(公告)号：US20070247889A1

公开(公告)日：2007-10-25

申请号：US11790009

申请日：2007-04-23

申请人： Takashi Miki ,  Yasuo Murakuki

发明人： Takashi Miki ,  Yasuo Murakuki

IPC分类号： G11C17/00

CPC分类号： G11C11/22

摘要： A semiconductor memory device is provided with plural memory cells, plural bit lines BL, each bit line being commonly connected to the plural memory cells that are arranged in the same row, plural word lines WL and plural plate lines CP, each word line and each plate line being commonly connected to the plural memory cells that are arranged in the same column, plural plate voltage supply lines CPS arranged in the column direction, and means for electrically connecting each of the plural plate voltage supply lines to each of the corresponding plural plate lines. The plate voltage supply lines are composed of a material having a resistance lower than that of the plate lines, each of capacitors of the plural memory cells is covered with a hydrogen barrier film HB at its periphery, the plural plate voltage supply lines are disposed beneath the hydrogen barrier film HB, and the plural plate voltage supply lines CPS are, when viewed in a plane, electrically connected to the same plate line at plural positions of the same plate line, within a region where the hydrogen barrier film is disposed.

摘要翻译： 半导体存储器件具有多个存储单元，多个位线BL，每个位线共同连接到排列在同一行的多个存储单元，多个字线WL和多个板条CP，每个字线和每个 板线通常连接到布置在同一列中的多个存储单元，沿列方向排列的多个板电压供给线CPS，以及用于将多个板电压供给线中的每一个电连接到相应的多个板中的每一个的装置 线条。 板电压供给线由具有低于板线电阻的材料构成，多个存储单元的每个电容器在其周边被氢阻挡膜HB覆盖，多个板电压供给线设置在 在与设置有氢阻挡膜的区域相同的板线的多个位置上的同一板线电连接的情况下，氢阻挡膜HB和多个板电压供给线CPS为同一平面。

公开(公告)号：US20050265090A1

公开(公告)日：2005-12-01

申请号：US11121939

申请日：2005-05-05

申请人： Yasuo Murakuki ,  Hiroshige Hirano ,  Yasushi Gohou ,  Masahiko Sakagami ,  Kunisato Yamaoka ,  Shunichi Iwanari ,  Tetsuji Nakakuma ,  Takashi Miki

发明人： Yasuo Murakuki ,  Hiroshige Hirano ,  Yasushi Gohou ,  Masahiko Sakagami ,  Kunisato Yamaoka ,  Shunichi Iwanari ,  Tetsuji Nakakuma ,  Takashi Miki

IPC分类号： G11C11/22 ,  G11C7/00 ,  G11C29/00 ,  G11C29/12

CPC分类号： G11C29/816 ,  G11C11/22 ,  G11C29/789 ,  G11C2029/4402

摘要： To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost. A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.

摘要翻译： 为了提供可以适应涉及不同处理温度的装配过程的半导体存储装置，当用户重写数据被禁止时，可以变得不可改变，否定了开发不同的半导体存储装置的必要性，并且降低了开发成本。 半导体存储装置设置有用于存储指示故障区域的有缺陷的地址信息和关于半导体存储装置的操作模式设置信息的区域，由可重写非易失性存储器和第二设置功能存储器形成的第一设置功能存储区域103 区域102由一次性可重写的非易失性存储器形成。 选择性地执行将故障地址信息传送到故障地址寄存器111和将操作模式设置信息传送到操作模式寄存器110。

公开(公告)号：USRE41879E1

公开(公告)日：2010-10-26

申请号：US12155392

申请日：2008-06-03

申请人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

发明人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

IPC分类号： G11C16/06

CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1063 ,  G11C2207/229

摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.

摘要翻译： 提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。 当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。 同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。 当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

公开(公告)号：US20100023840A1

公开(公告)日：2010-01-28

申请号：US12480294

申请日：2009-06-08

申请人： Yoshiaki Nakao ,  Yasushi Gohou ,  Shunichi Iwanari ,  Masanori Matsuura ,  Yasuo Murakuki

发明人： Yoshiaki Nakao ,  Yasushi Gohou ,  Shunichi Iwanari ,  Masanori Matsuura ,  Yasuo Murakuki

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/13 ,  G06F11/1008 ,  H03M13/19

摘要： A syndrome generation section generates a syndrome from input data having d bits of data bits and k bits of parity bits. A syndrome table stores a syndrome pattern indicating that no error has occurred in the input data and syndrome patterns indicating an error position. A comparison section compares the syndrome generated by the syndrome generation section with the syndrome patterns in the syndrome table, outputs a match signal when a syndrome pattern matching the syndrome exists, and outputs a no-match signal when no syndrome pattern matching the syndrome exists. An error correction section corrects the error in the input data based on the match signal from the comparison section.

摘要翻译： 校正子产生部分从具有数据位d位和奇偶校验位k位的输入数据生成校正子。 校正子表存储指示在输入数据中没有发生错误的校正子模式和指示错误位置的校正子模式。 比较部分将由校正子产生部分产生的综合征与综合征表中的综合征模式进行比较，当不存在匹配该综合征的综合征模式时，输出匹配信号，并且当不存在与该综合征相匹配的症状模式时，输出不匹配信号。 误差校正部分根据比较部分的匹配信号校正输入数据中的误差。

公开(公告)号：US07136313B2

公开(公告)日：2006-11-14

申请号：US11121939

申请日：2005-05-05

申请人： Yasuo Murakuki ,  Hiroshige Hirano ,  Yasushi Gohou ,  Masahiko Sakagami ,  Kunisato Yamaoka ,  Shunichi Iwanari ,  Tetsuji Nakakuma ,  Takashi Miki

发明人： Yasuo Murakuki ,  Hiroshige Hirano ,  Yasushi Gohou ,  Masahiko Sakagami ,  Kunisato Yamaoka ,  Shunichi Iwanari ,  Tetsuji Nakakuma ,  Takashi Miki

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C29/816 ,  G11C11/22 ,  G11C29/789 ,  G11C2029/4402

摘要： To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost.A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.

摘要翻译： 为了提供可以适应涉及不同处理温度的装配过程的半导体存储装置，当用户重写数据被禁止时，可以变得不可改变，否定了开发不同的半导体存储装置的必要性，并且降低了开发成本。 半导体存储装置设置有用于存储指示故障区域的有缺陷的地址信息和关于半导体存储装置的操作模式设置信息的区域，由可重写非易失性存储器和第二设置功能存储器形成的第一设置功能存储区域103 区域102由一次性可重写的非易失性存储器形成。 选择性地执行将故障地址信息传送到故障地址寄存器111和将操作模式设置信息传送到操作模式寄存器110。

公开(公告)号：US07016247B2

公开(公告)日：2006-03-21

申请号：US11023663

申请日：2004-12-29

申请人： Yasuo Murakuki ,  Masahiko Sakagami ,  Shunichi Iwanari

发明人： Yasuo Murakuki ,  Masahiko Sakagami ,  Shunichi Iwanari

IPC分类号： G11C7/00

CPC分类号： G11C17/18 ,  G11C29/785

摘要： A semiconductor memory apparatus including a simple circuit configuration and is capable of randomly accessing fuse data. A fuse cell 30 including a fuse 31 is connected to a pair of bit lines of a memory circuit. The fuse 31 and a fuse data output circuit (which includes a resistor 32 and an inverter 33) are connected to a pair of bit lines BLT and BLB of the memory circuit through a fuse selection switch 34. By allowing a column decoder 12 for selecting a pair of bit lines of the memory cell to also function as a decoder circuit for selecting a fuse, the bit lines of the memory circuit can be used as signal lines for outputting fuse data, whereby the circuit size is reduced and the circuit area is reduced.

摘要翻译： 一种半导体存储装置，包括简单的电路结构，能够随机访问熔丝数据。 包括熔丝31的熔丝单元30连接到存储电路的一对位线。 熔丝31和熔丝数据输出电路（其包括电阻32和反相器33）通过熔丝选择开关34连接到存储电路的一对位线BLT和BLB。 通过允许列解码器12选择存储器单元的一对位线也用作用于选择熔丝的解码器电路，存储电路的位线可以用作用于输出熔丝数据的信号线，由此电路 尺寸减小，电路面积减小。

公开(公告)号：US20090244951A1

公开(公告)日：2009-10-01

申请号：US12368622

申请日：2009-02-10

申请人： Yasuo MURAKUKI ,  Yasushi GOHOU ,  Shunichi IWANARI ,  Masanori MATSUURA ,  Yoshiaki NAKAO

发明人： Yasuo MURAKUKI ,  Yasushi GOHOU ,  Shunichi IWANARI ,  Masanori MATSUURA ,  Yoshiaki NAKAO

IPC分类号： G11C11/22 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C11/22

摘要： A semiconductor memory device includes a plurality of memory cell arrays each including a plurality of memory cells arranged in a matrix pattern, and a plurality of cell plate lines each being shared by the memory cell arrays, each of the cell plate lines corresponding to each of rows of the memory cells and each of the cell plate lines being connected to the memory cells of a corresponding one of the rows. Each of the memory cell arrays includes a plurality of word lines each of which corresponds to each of the rows of the memory cells in the memory cell array. The number of the memory cells connected to each of the cell plate lines is larger than the number of the memory cells connected to one of the word lines corresponding to the each of the cell plate lines.

摘要翻译： 半导体存储器件包括多个存储单元阵列，每个存储单元阵列包括以矩阵图案排列的多个存储单元，以及多个存储单元阵列共享的单元板板线，每个单元板线对应于 存储单元的行和每个单元格板线连接到相应行之一的存储单元。 每个存储单元阵列包括多个字线，每个字线对应于存储单元阵列中存​​储单元的行中的每一行。 连接到每个单元格板行的存储单元的数量大于连接到与每个单元格板行相对应的一个字线的存储单元的数量。

公开(公告)号：US20070195578A1

公开(公告)日：2007-08-23

申请号：US11707157

申请日：2007-02-16

申请人： Yasuo Murakuki ,  Takashi Miki

发明人： Yasuo Murakuki ,  Takashi Miki

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A memory cell array is composed of a plurality of memory cells arranged in a matrix. Each of the memory cells includes: a capacitor having a plate electrode connected to a common cell plate and a storage electrode; and a transistor provided between the storage electrode of the capacitor and a bit line, with a gate connected to a word line. A first amplifier amplifies an I/O line pair to a first voltage and a second voltage higher than the first voltage. A second amplifier amplifies a bit line pair to the first voltage and a third voltage higher than the second voltage. A switch element switches the connection relationship between the I/O line pair and the bit line pair among a connected state, a disconnected state and a transmission limited state in which the potential transmitted is limited.

摘要翻译： 存储单元阵列由以矩阵排列的多个存储单元组成。 每个存储单元包括：具有连接到公共单元板和存储电极的平板电极的电容器; 以及设置在电容器的存储电极和位线之间的晶体管，栅极连接到字线。 第一放大器将I / O线对放大到高于第一电压的第一电压和第二电压。 第二放大器将位线对放大到第一电压和高于第二电压的第三电压。 开关元件在连接状态，断开状态和限制发送电位的发送限制状态之间切换I / O线对与位线对之间的连接关系。