- 专利标题: LSI design method and verification method
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申请号: US11520712申请日: 2006-09-14
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公开(公告)号: US20070011468A1公开(公告)日: 2007-01-11
- 发明人: Kentaro Shiomi , Akira Motohara , Makoto Fujiwara , Toshiyuki Yokoyama , Katsuya Fujimura
- 申请人: Kentaro Shiomi , Akira Motohara , Makoto Fujiwara , Toshiyuki Yokoyama , Katsuya Fujimura
- 申请人地址: JP Osaka
- 专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人地址: JP Osaka
- 优先权: JP2000-034577 20000214
- 主分类号: G06F12/14
- IPC分类号: G06F12/14
摘要:
An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.
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