公开(公告)号：US20090106721A1

公开(公告)日：2009-04-23

申请号：US12334988

申请日：2008-12-15

申请人： Sadami TAKEOKA ,  Takahiro ICHINOMIYA ,  Akira MOTOHARA

发明人： Sadami TAKEOKA ,  Takahiro ICHINOMIYA ,  Akira MOTOHARA

IPC分类号： G06F17/50

CPC分类号： G01R31/318586

摘要： A method of designing a semiconductor integrated circuit includes steps of selecting a pair of scan registers to be connected as a scan chain and calculating a beeline distance on hardware from each output terminal of the scan register at the front stage to a scan data input terminal of the scan register at the rear stage. The method further includes steps of selecting the output terminal of the scan register at the front stage having a minimum beeline distance on the basis of the above calculation; determining to connect the selected output terminal with the scan data input terminal of the scan register at the rear stage; and forming the scan chain by connecting each pair of scan registers by using the output terminal determined in the previous step.

摘要翻译： 一种设计半导体集成电路的方法包括以下步骤：选择要作为扫描链连接的一对扫描寄存器，并计算硬件上从前级扫描寄存器的每个输出端到扫描数据输入端的扫描数据输入端 后级扫描寄存器。 该方法还包括以下步骤：基于上述计算，在具有最小直线距离的前级选择扫描寄存器的输出端; 确定将所选输出端与后级扫描寄存器的扫描数据输入端连接; 以及通过使用在前一步骤中确定的输出端子连接每对扫描寄存器来形成扫描链。

公开(公告)号：US06668337B2

公开(公告)日：2003-12-23

申请号：US09864285

申请日：2001-05-25

申请人： Miwaka Takahashi ,  Akira Motohara ,  Osamu Ogawa

发明人： Miwaka Takahashi ,  Akira Motohara ,  Osamu Ogawa

IPC分类号： G06F1750

CPC分类号： G06F17/5045 ,  G06F2217/78

摘要： Architecture design (AD), architecture floorplanning (AF), and transaction analysis (TA) are performed before transaction-analysis-based floorplanning (TF). Then, area estimation (CE) is performed on functional parts and connections before area-based floorplanning (CF) and area optimization (CO) are performed, and whether or not the area specifications area satisfied or not is validated (CR). Besides, power consumption estimation (PE) is performed to check whether or not the power consumption specifications are satisfied (PR). In the case of taking a parallelization approach to realize lower power consumption, parallelization design (PD) is performed. After the power consumption specifications are satisfied, power supply wiring/floorplanning is performed.

摘要翻译： 架构设计（AD），架构布局规划（AF）和事务分析（TA）在基于交易分析的布图规划（TF）之前进行。 然后，在执行基于区域的布局规划（CF）和区域优化（CO）之前以及是否验证区域规格区域（CR）是否对功能部件和连接进行区域估计（CE）。 此外，进行功耗估计（PE）以检查功耗规格是否满足（PR）。 在采用并行化方法实现较低功耗的情况下，执行并行化设计（PD）。 在满足功耗规格后，进行电源配线/布局规划。

公开(公告)号：US06415416B1

公开(公告)日：2002-07-02

申请号：US09418312

申请日：1999-10-14

申请人： Makoto Fujiwara ,  Akira Motohara ,  Toshiyuki Yokoyama

发明人： Makoto Fujiwara ,  Akira Motohara ,  Toshiyuki Yokoyama

IPC分类号： G06F1750

CPC分类号： G06F17/5045

摘要： Information about an exclusive operation among a plurality of blocks and interconnection information about a sharable resource within each of these blocks are defined. Based on the sharable resource information and the inter-block exclusive operation information, a resource sharable among the blocks is extracted. Module specifications, in which information about interfaces, power dissipation, operation models and top-level hierarchy interconnection is stored, exclusive operation information describing an exclusive operation rule among the blocks, and prioritized function information used for preventing respective functions from being enabled at the same time are input to an generator, which is an automatic generating tool. In this manner, a power and clock management module for use in power save management, a wrapper bank select module storing interconnection information, a shared resource module storing information about a sharable resource and an optimized top-level hierarchy module storing interconnection information about an optimized top-level hierarchy are generated. Downsizing and power saving are realized by resource sharing and power management.

摘要翻译： 关于多个块中的排他性操作的信息和关于每个这些块内的可共享资源的互连信息被定义。 基于可共享资源信息和块间专用操作信息，提取在块之间可共享的资源。 存储关于接口，功耗，操作模型和顶级层级互连的信息的模块规格，描述块之间的排他性操作规则的排他性操作信息，以及用于防止各功能在相同功能中被使能的优先功能信息 时间被输入到作为自动生成工具的发电机。 以这种方式，用于节电管理的电源和时钟管理模块，存储互连信息的封装器组选择模块，存储关于可共享资源的信息的共享资源模块和存储关于优化的互连信息的优化顶层层级模块 生成顶级层次结构。 资源共享和电源管理实现了小型化和省电化。

公开(公告)号：US5729553A

公开(公告)日：1998-03-17

申请号：US684066

申请日：1996-07-19

申请人： Akira Motohara

发明人： Akira Motohara

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318536

摘要： Three blocks cascaded to one another in an LSI, namely, an input module, a macro module and an output module, are independently tested. A first test circuit is formed with a first multiplexer interposed between the macro module and the output module, and a second multiplexer and a first control register interposed between the input module and the macro module. A second test circuit is similarly formed with third and fourth multiplexers and a second control register. A test input signal of a plurality of bits is supplied to the first multiplexer, and a latched signal of the first control register is supplied to the third multiplexer, thereby allowing a latched signal of the second control register to be output as a test output signal for observation. Thus, testing techniques requiring a small additional circuit and a small number of additional wires for the test can be provided.

公开(公告)号：US5617427A

公开(公告)日：1997-04-01

申请号：US544162

申请日：1995-10-17

申请人： Mitsuyasu Ohta ,  Akira Motohara

发明人： Mitsuyasu Ohta ,  Akira Motohara

IPC分类号： G01R31/3185 ,  G06F11/00

CPC分类号： G01R31/31855

摘要： This invention is intended for a semiconductor integrated circuit with scan logical blocks wherein scan flip-flops are used for interblock signal communication. A testing sequence is generated to detect a fault in a target scan logical block. First, a block testing sequence, which is a testing sequence to the scan logical block as a single circuit, is generated. If signal inversion occurs in a scan chain that runs through the scan logical block, data that is inputted to or outputted from the scan logical block via such a scan chain is inverted. Patterns equal in number to the semiconductor integrated circuit's structure are placed in front of and behind a shift-in pattern and a shift-out pattern in the block testing sequence, to convert the block testing sequence into a testing sequence for the entire semiconductor integrated circuit. Upon completion of all the testing sequence generation with respect to the scan logical blocks, the generated testing sequences are merged.

摘要翻译： 本发明旨在用于具有扫描逻辑块的半导体集成电路，其中扫描触发器用于帧间信号通信。 生成测试序列以检测目标扫描逻辑块中的故障。 首先，生成作为单个电路的扫描逻辑块的测试序列的块测试序列。 如果在穿过扫描逻辑块的扫描链中发生信号反转，则通过这样的扫描链输入或从扫描逻辑块输出的数据被反转。 将数量与半导体集成电路结构相等的图案放置在块测试序列中的移位模式和移出模式的前面和后面，将块测试序列转换成整个半导体集成电路的测试序列 。 在完成关于扫描逻辑块的所有测试序列生成之后，生成的测试序列被合并。

公开(公告)号：US5483543A

公开(公告)日：1996-01-09

申请号：US948353

申请日：1992-09-23

申请人： Toshinori Hosokawa ,  Akira Motohara ,  Mitsuyasu Ohta

发明人： Toshinori Hosokawa ,  Akira Motohara ,  Mitsuyasu Ohta

IPC分类号： G01R31/3183 ,  G06F11/22 ,  G06F11/26 ,  G06F17/50 ,  G06F11/27 ,  G06F11/273

CPC分类号： G01R31/318392 ,  G01R31/318371

摘要： A method for generating a test sequence for a fault in a sequential circuit to provide high fault coverage. In one embodiment (FIG. 1), a circuit state, which a system fails to justify, is stored as an illegal state in a step 107. In a step 103, a target fault is selected. In a step 104, the system performs its fault propagation processing to generate a test sequence and propagate the target fault from a fault location to any external output pin in such a manner that the circuit state does not coincide with the illegal state set stored in the step 107, and judges the success or failure of the sequence generation. In a step 105, the system performs its state initialization processing to generate a test sequence and transfer the state of the circuit from its initial state to a state when the fault was sensitized in such a manner that the circuit state does not coincide with the illegal state set stored in the step 107, and judges the success or failure of the sequence generation. Since the circuit state when the system fails to justify the state is stored as the illegal state so that a circuit state at the time of generating a subsequent test sequence is prevented from coinciding with the illegal state set, the possibility of the successful test sequence generation can be increased and thus the test sequence generation system can achieve high fault coverage.

摘要翻译： 一种用于为顺序电路中的故障产生测试序列以提供高故障覆盖的方法。 在一个实施例（图1）中，系统无法证明的电路状态在步骤107中被存储为非法状态。在步骤103中，选择目标故障。 在步骤104中，系统执行其故障传播处理，以产生测试序列，并将目标故障从故障位置传播到任何外部输出引脚，使得电路状态与存储在 步骤107，判断序列生成的成败。 在步骤105中，系统执行其状态初始化处理以产生测试序列，并将电路的状态从其初始状态转移到故障致敏状态，使得电路状态与非法 状态集合，并且判断序列生成的成败。 由于当系统无法证明状态时的电路状态被存储为非法状态，使得在生成后续测试序列时的电路状态被阻止与非法状态集合一致，成功的测试序列生成的可能性 可以增加测试序列生成系统，从而可以实现高故障覆盖。

公开(公告)号：US20080028233A1

公开(公告)日：2008-01-31

申请号：US11601776

申请日：2006-11-20

申请人： Kentaro Shiomi ,  Akira Motohara ,  Makoto Fujiwara ,  Toshiyuki Yokoyama ,  Katsuya Fujimura

发明人： Kentaro Shiomi ,  Akira Motohara ,  Makoto Fujiwara ,  Toshiyuki Yokoyama ,  Katsuya Fujimura

IPC分类号： G06F12/14 ,  H04L9/32 ,  G06F11/30

CPC分类号： G06F21/75 ,  G06F17/5022 ,  G06F21/6209

摘要： An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.

摘要翻译： 在LSI设计中采用加密处理，以便改进电路设计数据与传统示例的机密性。 在加密过程中，机密电路设计数据被加密以产生加密设计数据和加密密钥。 将加密的设计数据提供给进行设计/验证处理的用户。 钥匙也按要求提供。 在设计/验证过程中，对加密设计数据进行各种处理，而不会公开原始电路的内容。 在解码处理中，经受设计/验证处理的加密设计数据被解码以产生原始电路设计数据。

公开(公告)号：US07284134B2

公开(公告)日：2007-10-16

申请号：US10231376

申请日：2002-08-30

申请人： Makoto Fujiwara ,  Akira Motohara

发明人： Makoto Fujiwara ,  Akira Motohara

IPC分类号： G06F11/30

CPC分类号： G06F21/73 ,  G11C7/24 ,  G11C17/14 ,  G11C29/027 ,  G11C29/12 ,  G11C2029/5002

摘要： In an LSI, a decoding section decodes an ID signal received externally and outputs the decoded signal. A fuse circuit writes the value represented by the decoded signal therein when an operation setting signal is active, and holds the written value when the operation setting signal is inactive. An ID RAM stores the value held in the fuse circuit as the ID. This enables installation of IDs of various values in LSIs only by changing the value of the ID signal.

摘要翻译： 在LSI中，解码部对从外部接收的ID信号进行解码，并输出解码信号。 当操作设置信号有效时，熔丝电路将解码信号表示的值写入其中，并且当操作设置信号无效时保持写入值。 ID RAM将保存在熔丝电路中的值作为ID存储。 这样可以通过改变ID信号的值来在LSI中安装各种ID的ID。

公开(公告)号：US5894482A

公开(公告)日：1999-04-13

申请号：US890976

申请日：1997-07-10

申请人： Akira Motohara

发明人： Akira Motohara

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318536

摘要： Three blocks cascaded to one another in an LSI, namely, an input module, a macro module and an output module, are independently tested. A first test circuit is formed with a first multiplexer interposed between the macro module and the output module, and a second multiplexer and a first control register interposed between the input module and the macro module. A second test circuit is similarly formed with third and fourth multiplexers and a second control register. A test input signal of a plurality of bits is supplied to the first multiplexer, and a latched signal of the first control register is supplied to the third multiplexer, thereby allowing a latched signal of the second control register to be output as a test output signal for observation. Thus, testing techniques requiring a small additional circuit and a small number of additional wires for the test can be provided.

摘要翻译： 在LSI中彼此级联的三个块，即输入模块，宏模块和输出模块被独立测试。 第一测试电路形成有插入在宏模块和输出模块之间的第一多路复用器，以及插入在输入模块和宏模块之间的第二多路复用器和第一控制寄存器。 第二测试电路与第三和第四多路复用器和第二控制寄存器类似地形成。 多个比特的测试输入信号被提供给第一多路复用器，并且第一控制寄存器的锁存信号被提供给第三多路复用器，从而允许输出第二控制寄存器的锁存信号作为测试输出信号 用于观察。 因此，可以提供需要小的附加电路和少量用于测试的附加电线的测试技术。

公开(公告)号：US5430736A

公开(公告)日：1995-07-04

申请号：US868737

申请日：1992-04-15

申请人： Sadami Takeoka ,  Akira Motohara

发明人： Sadami Takeoka ,  Akira Motohara

IPC分类号： G01R31/3183 ,  G01R31/28 ,  G01R31/3185 ,  G06F11/22 ,  G06F11/263

CPC分类号： G01R31/318586 ,  G01R31/318547 ,  G01R31/318392

摘要： In an apparatus for generating a test pattern for a sequential logic circuit including a plurality of storage elements each storage element storing a logical value of one bit wherein logical values of bits of the plurality of storage elements being represented by a state, first external input values are generated so that a transition process is performed from a second state of the plurality of storage elements to a first state thereof, and second external input values are generated so hat a transition process is performed from a third state of the plurality of storage elements to the first state thereof. Thereafter, third external input values are generated so that a transition process is performed from a fourth state of the plurality of storage elements to the first state thereof. After setting the fourth state as the first state, name data of storage elements corresponding to bits of different states between the second and third states are stored in a storage unit. After setting the third state as the first state, there is increased a degree of requesting a scan operation for each of the storage elements, name data of which have been stored in the storage unit. Then, storage elements to be scanned are selected for generating an improved test pattern based on the degree of requesting the scan operation.

摘要翻译： 在用于生成包括多个存储元件的顺序逻辑电路的测试图案的装置中，每个存储元件存储一位的逻辑值，其中多个存储元件的位的逻辑值由状态表示，第一外部输入值 被产生，使得从多个存储元件的第二状态到其第一状态执行转换处理，并且产生第二外部输入值，从而从多个存储元件的第三状态执行转换处理， 其第一个状态。 此后，产生第三外部输入值，使得从多个存储元件的第四状态到其第一状态执行转换处理。 在将第四状态设置为第一状态之后，将与第二状态和第三状态之间的不同状态的位对应的存储元件的名称数据存储在存储单元中。 在将第三状态设置为第一状态之后，对存储单元中已存储的每个存储元件的每个存储元件请求扫描操作的程度增加。 然后，选择要扫描的存储元件，以便基于请求扫描操作的程度产生改进的测试图案。