Embodiments of the invention include an integrated circuit including a phase-locked loop (PLL). The integrated circuit includes a phase detector, a frequency detector, a loop filter, a digitally-controlled oscillator and a corresponding plurality of frequency dividers. The phase detector generates a first binary output based on a phase comparison of a reference clock signal to a plurality of clock phase inputs. The frequency detector generates a second binary output based on a frequency comparison of the reference clock signal to the clock phase inputs. The loop filter generates a third binary output based on the first binary output and the second binary output. The DCO feeds back the clock phase inputs, via the frequency dividers, to the phase detector based on the third binary output, and feeds back one of the clock phases to the frequency detector based on the third binary output.