公开(公告)号：US07808329B2

公开(公告)日：2010-10-05

申请号：US12187701

申请日：2008-08-07

申请人： Kameran Azadet ,  Fuji Yang

发明人： Kameran Azadet ,  Fuji Yang

IPC分类号： H03K3/03 ,  H03B27/00

CPC分类号： H03B27/00

摘要： Methods and apparatus are provided for improved phase linearity in a multi-phase based clock/timing recovery system. Averaging and interpolation techniques improve phase linearity in a multi-phase clock system. A multi-phase output clock is generated in accordance with one aspect of the invention by generating a plurality of clocks each having a substantially similar frequency and a different phase; applying each of the plurality of clocks to at least one corresponding amplifier such as a differential pair circuit; and summing an output of the corresponding amplifiers to generate the multi-phase output clock. A multiple-stage averaging operation can provide further linearity improvements.

摘要翻译： 提供了用于在多相时钟/定时恢复系统中改善相位线性度的方法和装置。 平均和内插技术提高了多相时钟系统的相位线性度。 根据本发明的一个方面，通过产生多个具有基本相似的频率和不同相位的时钟来产生多相输出时钟; 将多个时钟中的每一个施加到至少一个对应的放大器，例如差分对电路; 并对相应放大器的输出求和以产生多相输出时钟。 多级平均操作可以进一步提高线性度。

公开(公告)号：US20070025490A1

公开(公告)日：2007-02-01

申请号：US11191895

申请日：2005-07-28

申请人： Kameran Azadet ,  Fuji Yang

发明人： Kameran Azadet ,  Fuji Yang

IPC分类号： H03D3/24

CPC分类号： H03L7/087 ,  H03L7/093 ,  H03L7/0995 ,  H03L2207/50

摘要： Embodiments of the invention include an integrated circuit including a phase-locked loop (PLL). The integrated circuit includes a phase detector, a frequency detector, a loop filter, a digitally-controlled oscillator and a corresponding plurality of frequency dividers. The phase detector generates a first binary output based on a phase comparison of a reference clock signal to a plurality of clock phase inputs. The frequency detector generates a second binary output based on a frequency comparison of the reference clock signal to the clock phase inputs. The loop filter generates a third binary output based on the first binary output and the second binary output. The DCO feeds back the clock phase inputs, via the frequency dividers, to the phase detector based on the third binary output, and feeds back one of the clock phases to the frequency detector based on the third binary output.

摘要翻译： 本发明的实施例包括包括锁相环（PLL）的集成电路。 集成电路包括相位检测器，频率检测器，环路滤波器，数字控制振荡器和相应的多个分频器。 相位检测器基于参考时钟信号与多个时钟相位输入的相位比较来产生第一二进制输出。 频率检测器基于参考时钟信号与时钟相位输入的频率比较产生第二二进制输出。 环路滤波器基于第一个二进制输出和第二个二进制输出产生第三个二进制输出。 基于第三个二进制输出，DCO通过分频器将时钟相位输入反馈到相位检测器，并且基于第三个二进制输出将一个时钟相位反馈到频率检测器。

公开(公告)号：US20060017468A1

公开(公告)日：2006-01-26

申请号：US11141337

申请日：2005-05-31

申请人： Kameran Azadet ,  Fuji Yang ,  Chunbing Guo

发明人： Kameran Azadet ,  Fuji Yang ,  Chunbing Guo

IPC分类号： H03K19/094

CPC分类号： H04L25/0282 ,  H03K19/09432 ,  H04L25/0274

摘要： A common-mode shifting circuit for shifting the common-mode output voltage of a CML device to an arbitrary voltage is disclosed. A constant current source is provided at each output of the CML device. The constant current may be a positive or negative current, tending to raise or lower the common-mode output voltage, respectively. The constant current sources are preferably connected to an alternate voltage supply having a higher voltage than that the supply for the CML device. The invention further provides a method for adjusting the output signal of a current-mode logic circuit having two or more output ports, comprising the step of providing a constant current at each output port of the current-mode logic circuit, whereby the common-mode voltage at the output ports of said current-mode logic circuit is level-shifted.

摘要翻译： 公开了一种用于将CML器件的共模输出电压转换为任意电压的共模移位电路。 在CML设备的每个输出端提供恒流源。 恒定电流可以是正或负电流，分别提高或降低共模输出电压。 恒流源优选地连接到具有比CML器件的电源高的电压的交流电压源。 本发明还提供一种用于调整具有两个或多个输出端口的电流模式逻辑电路的输出信号的方法，包括在电流模式逻辑电路的每个输出端口处提供恒定电流的步骤，由此共模 所述电流模式逻辑电路的输出端口处的电压被电平移位。

公开(公告)号：US20100034333A1

公开(公告)日：2010-02-11

申请号：US12187701

申请日：2008-08-07

申请人： Kameran Azadet ,  Fuji Yang

发明人： Kameran Azadet ,  Fuji Yang

IPC分类号： H03D3/24

CPC分类号： H03B27/00

摘要： Methods and apparatus are provided for improved phase linearity in a multi-phase based clock/timing recovery system. Averaging and interpolation techniques improve phase linearity in a multi-phase clock system. A multi-phase output clock is generated in accordance with one aspect of the invention by generating a plurality of clocks each having a substantially similar frequency and a different phase; applying each of the plurality of clocks to at least one corresponding amplifier such as a differential pair circuit; and summing an output of the corresponding amplifiers to generate the multi-phase output clock. A multiple-stage averaging operation can provide further linearity improvements.

摘要翻译： 提供了用于在多相时钟/定时恢复系统中改善相位线性度的方法和装置。 平均和内插技术提高了多相时钟系统的相位线性度。 根据本发明的一个方面，通过产生多个具有基本相似的频率和不同相位的时钟来产生多相输出时钟; 将多个时钟中的每一个施加到至少一个对应的放大器，例如差分对电路; 并对相应放大器的输出求和以产生多相输出时钟。 多级平均操作可以进一步提高线性度。

公开(公告)号：US07577225B2

公开(公告)日：2009-08-18

申请号：US11191895

申请日：2005-07-28

申请人： Kameran Azadet ,  Fuji Yang

发明人： Kameran Azadet ,  Fuji Yang

IPC分类号： H03D3/24

CPC分类号： H03L7/087 ,  H03L7/093 ,  H03L7/0995 ,  H03L2207/50

摘要： Embodiments of the invention include an integrated circuit including a phase-locked loop (PLL). The integrated circuit includes a phase detector, a frequency detector, a loop filter, a digitally-controlled oscillator and a corresponding plurality of frequency dividers. The phase detector generates a first binary output based on a phase comparison of a reference clock signal to a plurality of clock phase inputs. The frequency detector generates a second binary output based on a frequency comparison of the reference clock signal to the clock phase inputs. The loop filter generates a third binary output based on the first binary output and the second binary output. The DCO feeds back the clock phase inputs, via the frequency dividers, to the phase detector based on the third binary output, and feeds back one of the clock phases to the frequency detector based on the third binary output.

摘要翻译： 本发明的实施例包括包括锁相环（PLL）的集成电路。 集成电路包括相位检测器，频率检测器，环路滤波器，数字控制振荡器和相应的多个分频器。 相位检测器基于参考时钟信号与多个时钟相位输入的相位比较来产生第一二进制输出。 频率检测器基于参考时钟信号与时钟相位输入的频率比较产生第二二进制输出。 环路滤波器基于第一个二进制输出和第二个二进制输出产生第三个二进制输出。 基于第三个二进制输出，DCO通过分频器将时钟相位输入反馈到相位检测器，并且基于第三个二进制输出将一个时钟相位反馈到频率检测器。

公开(公告)号：US07355451B2

公开(公告)日：2008-04-08

申请号：US11141337

申请日：2005-05-31

申请人： Kameran Azadet ,  Fuji Yang ,  Chunbing Guo

发明人： Kameran Azadet ,  Fuji Yang ,  Chunbing Guo

IPC分类号： H03K19/0175

CPC分类号： H04L25/0282 ,  H03K19/09432 ,  H04L25/0274

摘要： A common-mode shifting circuit for shifting the common-mode output voltage of a CML device to an arbitrary voltage is disclosed. A constant current source is provided at each output of the CML device. The constant current may be a positive or negative current, tending to raise or lower the common-mode output voltage, respectively. The constant current sources are preferably connected to an alternate voltage supply having a higher voltage than that the supply for the CML device. The invention further provides a method for adjusting the output signal of a current-mode logic circuit having two or more output ports, comprising the step of providing a constant current at each output port of the current-mode logic circuit, whereby the common-mode voltage at the output ports of said current-mode logic circuit is level-shifted.

摘要翻译： 公开了一种用于将CML器件的共模输出电压转换为任意电压的共模移位电路。 在CML设备的每个输出端提供恒流源。 恒定电流可以是正或负电流，分别提高或降低共模输出电压。 恒流源优选地连接到具有比CML器件的电源高的电压的交流电压源。 本发明还提供一种用于调整具有两个或多个输出端口的电流模式逻辑电路的输出信号的方法，包括在电流模式逻辑电路的每个输出端口处提供恒定电流的步骤，由此共模 所述电流模式逻辑电路的输出端口处的电压被电平移位。

公开(公告)号：US07164711B2

公开(公告)日：2007-01-16

申请号：US10348871

申请日：2003-01-22

申请人： Fuji Yang ,  Fadi Saibi ,  Chunbing Guo ,  Kameran Azadet

发明人： Fuji Yang ,  Fadi Saibi ,  Chunbing Guo ,  Kameran Azadet

IPC分类号： H03H7/30 ,  H04B3/14

CPC分类号： H04L25/03885

摘要： A digitally programmable analog receive-side channel equalizer includes N identical zero-positioning (ZP) circuit pairs in a cascade, where the transfer function of one ZP circuit of each pair exhibits a positive zero and the transfer function of the other ZP circuit exhibits a negative zero. By digitally controlling tunable capacitors within the pairs, the equalizer's frequency response and gain can be adjusted, while a controllable (e.g., constant) group delay is maintained. The number of blocks in the cascade can be selected, and each block independently configured, to optimally compensate for high-frequency losses in a wide range of transmission environments. One implementation involves a T-block cascade with output taps that feed a T:1 output selector such that the output of the overall equalizer can be selected to be any one of these taps corresponding to a programmable equalizer of effective length N where N≦T.

摘要翻译： 数字可编程模拟接收侧信道均衡器包括级联中的N个相同的零定位（ZP）电路对，其中每对一个ZP电路的传递函数呈现正零，并且另一个ZP电路的传递函数呈现为 负零。 通过数字地控制成对内的可调谐电容器，可以调节均衡器的频率响应和增益，同时保持可控（例如，恒定的）组延迟。 可以选择级联中的块数，并且每个块独立配置，以最佳地补偿广泛传输环境中的高频损耗。 一个实现涉及具有输出抽头的T块级联，其输入T：1输出选择器，使得总均衡器的输出可以被选择为对应于有效长度N的可编程均衡器的任何一个，其中N < T.

公开(公告)号：US09170776B2

公开(公告)日：2015-10-27

申请号：US12362899

申请日：2009-01-30

申请人： Kameran Azadet ,  Jian-Guo Chen ,  Samer Hijazi ,  Joseph Williams

发明人： Kameran Azadet ,  Jian-Guo Chen ,  Samer Hijazi ,  Joseph Williams

IPC分类号： G06F1/035 ,  G06F7/556 ,  G06F1/03

CPC分类号： G06F7/556 ,  G06F1/0307 ,  G06F1/035 ,  G06F2101/10

摘要： A digital signal processor is provided having an instruction set with a logarithm function that uses a reduced look-up table. The disclosed digital signal processor evaluates a logarithm function for an input value, x, by decomposing the input value, x, to a first part, N, a second part, q, and a remaining part, r, wherein the first part, N, is identified by a position of a most significant bit of the input value, x, and the second part, q, is comprised of a number of bits following the most significant bit, wherein the number is small relative to a number of bits in the input value, x; obtaining a value Log 2 ⁡ ( 1 + 1 2 ⁢ q ) from a first look-up table based on the second part, q; computing an epsilon term, ε, using the expression 2 - N 1 + 1 2 ⁢ q ⁢ r ; evaluating an expression Log2 (1+ε) using a polynomial approximation, such as a cubic approximation; and determining the logarithm function for the input value, x, by summing the values of N, Log Z ⁡ ( 1 + 1 2 ⁢ q ) and Log2(1+ε).

摘要翻译： 提供一种数字信号处理器，其具有使用缩减的查找表的具有对数函数的指令集。 所公开的数字信号处理器通过将输入值x分解为第一部分N，第二部分q和剩余部分r来评估输入值x的对数函数，其中第一部分N 由输入值x的最高有效位的位置识别，第二部分q由最高有效位之后的位数组成，其中该数目相对于位数 输入值x; 基于第二部分从第一查找表获得值Log 2⁡（1 + 1 2 q）q; 使用表达式2-N 1 + 1 2 q r;计算ε项，＆egr; 使用诸如立方近似的多项式近似来评估表达式Log2（1 +＆egr;）; 并且通过将N，Log Z⁡（1 + 1 2 q）和Log2（1 +＆egr））的值求和来确定输入值x的对数函数。

公开(公告)号：US08799341B2

公开(公告)日：2014-08-05

申请号：US11781313

申请日：2007-07-23

申请人： Kameran Azadet

发明人： Kameran Azadet

IPC分类号： G06F17/10

CPC分类号： H03H17/06 ,  H03F1/32 ,  H03H2017/0692 ,  H03H2218/06

摘要： Multi-dimensional finite impulse response filters ale disclosed in hybrid and transpose forms. Multi-dimensional signals can be expressed in a vector (ox matrix) form to allow multi-dimensional signals to be processed collectively. Known hybrid and transpose FIR filters are extended to the multi-dimensional case to allow multi-dimensional signals to be processed with reduced redundancies. The input signals are vectors with multidimensional components. The disclosed FIR filters include multipliers that perform matrix multiplications with multiple coefficients, and adders for performing vector additions with multiple inputs and outputs. The z-transforms are provided for the disclosed hybrid and transpose multi-dimensional FIR filters.

摘要翻译： 混合和转置形式中公开的多维有限脉冲响应滤波器。 多维信号可以以向量（ox矩阵）形式表示，以允许集体处理多维信号。 已知的混合和转置FIR滤波器被扩展到多维情况，以允许以减少的冗余来处理多维信号。 输入信号是具有多维分量的向量。 所公开的FIR滤波器包括执行具有多个系数的矩阵乘法的乘法器和用于执行具有多个输入和输出的矢量加法的加法器。 为所公开的混合和转置多维FIR滤波器提供z变换。

公开(公告)号：US08635516B2

公开(公告)日：2014-01-21

申请号：US13302707

申请日：2011-11-22

申请人： Kameran Azadet ,  Erich F. Haratsch

发明人： Kameran Azadet ,  Erich F. Haratsch

IPC分类号： H03M13/03

CPC分类号： H04L25/03006 ,  H03M13/256 ,  H03M13/39 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/6331 ,  H04L25/03305

摘要： A method and apparatus are disclosed for performing joint equalization and decoding of multidimensional codes transmitted over multiple symbol durations. An RSSE scheme is disclosed that cancels the intrasymbol interference caused by other symbol components within the same multidimensional code symbol. The disclosed RSSE technique for multidimensional codes applies where the number of trellis code dimensions exceeds the number of channels. The disclosed RSSE decoder computes the intersymbol interference caused by previously decoded multidimensional code symbols and subtracts the intersymbol interference from the received signal. In addition, a branch metrics unit compensates for the intrasymbol interference caused by other symbol components within the same multidimensional code symbol.

摘要翻译： 公开了一种用于执行在多个符号持续时间上发送的多维码的联合均衡和解码的方法和装置。 公开了一种RSSE方案，其消除由同一多维码符号内的其他符号分量引起的内部符号干扰。 所披露的用于多维码的RSSE技术适用于网格码数量超过信道数量的地方。 所公开的RSSE解码器计算由先前解码的多维码符号引起的符号间干扰，并从接收信号中减去符号间干扰。 此外，分支度量单元补偿由相同的多维码符号内的其他符号分量引起的内部符号干扰。