发明申请
- 专利标题: Integrated circuit with low-stress under-bump metallurgy
- 专利标题(中): 低应力欠凸下冶金的集成电路
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申请号: US11198419申请日: 2005-08-05
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公开(公告)号: US20070029669A1公开(公告)日: 2007-02-08
- 发明人: Frank Stepniak , William Higdon
- 申请人: Frank Stepniak , William Higdon
- 主分类号: H01L23/48
- IPC分类号: H01L23/48 ; H01L23/52 ; H01L29/40
摘要:
An integrated circuit (IC) includes a semiconductor material, electronic circuitry formed on the semiconductor material, a contact layer formed on the electronic circuitry, a final passivation layer formed on the contact layer and an under-bump metallurgy (UBM) formed on at least a portion of the final passivation layer. The contact layer includes a plurality of contacts pads for providing external access to the electronic circuitry. The final passivation layer includes a plurality of windows that extend through the final passivation layer to the contact pads. The UBM includes an aluminum layer having a thickness of about 800 angstroms to about 1200 angstroms, a nickel/vanadium (Ni/V) layer having a thickness of about 800 angstroms to about 1200 angstroms and a copper (Cu) layer having a thickness of about 800 angstroms to about 1200 angstroms.
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