发明申请
US20070043895A1 Method and apparatus for row based power control of a microprocessor memory array
审中-公开
微处理器存储器阵列的基于行的功率控制的方法和装置
- 专利标题： Method and apparatus for row based power control of a microprocessor memory array
- 专利标题（中）： 微处理器存储器阵列的基于行的功率控制的方法和装置
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申请号： US11204417申请日： 2005-08-16
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公开(公告)号： US20070043895A1公开(公告)日： 2007-02-22
- 发明人: Chad Adams , Toru Asano , Sang Dhong , Takaaki Nakazato , Joel Silberman , Osamu Takahashi
- 申请人： Chad Adams , Toru Asano , Sang Dhong , Takaaki Nakazato , Joel Silberman , Osamu Takahashi
- 主分类号： G06F12/06
- IPC分类号： G06F12/06 ; G06F1/00
摘要：
An apparatus, a method, and a computer program are provided to efficiently use a microprocessor array. Typically, microprocessor arrays can be divided into multiple subarrays. Also, in the conventional arrays, each of the subarrays were engaged when the microprocessor array is used. To alleviate the power consumed by the microprocessor arrays, row selection logic is employed to engage only specific rows of subarrays. Therefore, power consumed by unused subarrys is saved.
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