Invention Application
- Patent Title: Dual silicide semiconductor fabrication process
- Patent Title (中): 双硅化物半导体制造工艺
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Application No.: US11213470Application Date: 2005-08-26
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Publication No.: US20070048985A1Publication Date: 2007-03-01
- Inventor: Dharmesh Jawarani , Chong-Cheng Fu , Mark Hall
- Applicant: Dharmesh Jawarani , Chong-Cheng Fu , Mark Hall
- Main IPC: H01L21/28
- IPC: H01L21/28

Abstract:
A semiconductor fabrication process includes forming a gate stack overlying semiconductor substrate. Source/drain regions are formed in the substrate laterally aligned to the gate stack. A hard mask is formed overlying a gate electrode of the gate stack. A first silicide is then formed selectively over the source/drain regions. After removing the hard mask, a second silicide is selectively formed on the gate electrode. The first silicide and the second silicide are different. Forming the gate stack may include forming a gate dielectric on the semiconductor substrate and a polysilicon gate electrode on the gate dielectric. The gate electrode may have a line width of less than 40 nm. Forming the second silicide may include forming nickel silicide in upper portions of the gate electrode.
Public/Granted literature
- US07235473B2 Dual silicide semiconductor fabrication process Public/Granted day:2007-06-26
Information query
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