Invention Application
US20070069293A1 Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
有权
用于将体积衬底上的平面和非平面CMOS晶体管和由此制成的制品集成的工艺
- Patent Title: Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
- Patent Title (中): 用于将体积衬底上的平面和非平面CMOS晶体管和由此制成的制品集成的工艺
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Application No.: US11238444Application Date: 2005-09-28
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Publication No.: US20070069293A1Publication Date: 2007-03-29
- Inventor: Jack Kavalieros , Justin Brask , Brian Doyle , Uday Shah , Suman Datta , Mark Doczy , Matthew Metz , Robert Chau
- Applicant: Jack Kavalieros , Justin Brask , Brian Doyle , Uday Shah , Suman Datta , Mark Doczy , Matthew Metz , Robert Chau
- Main IPC: H01L21/84
- IPC: H01L21/84 ; H01L27/12
Abstract:
A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.
Public/Granted literature
- US07479421B2 Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby Public/Granted day:2009-01-20
Information query
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