公开(公告)号：US20110097858A1

公开(公告)日：2011-04-28

申请号：US12658670

申请日：2010-02-12

Applicant: Mark Doczy ,  Nathan Baxter ,  Robert S. Chau ,  Kari Harkonen ,  Teemu Lang

Inventor： Mark Doczy ,  Nathan Baxter ,  Robert S. Chau ,  Kari Harkonen ,  Teemu Lang

IPC: H01L21/336

CPC classification number: H01L29/4966 ,  C04B35/5618 ,  C04B2235/722 ,  C04B2235/723 ,  C22C14/00 ,  C22C16/00 ,  C22C27/00 ,  C22C32/0084 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/6659

Abstract: Embodiments of a transition metal alloy having an n-type or p-type work function that does not significantly shift at elevated temperature. The disclosed transition metal alloys may be used as, or form a part of, the gate electrode in a transistor. Methods of forming a gate electrode using these transition metal alloys are also disclosed.

Abstract translation: 具有在升高的温度下不会显着移位的n型或p型功函的过渡金属合金的实施例。 公开的过渡金属合金可以用作晶体管中的栅电极，或者形成其中的一部分。 还公开了使用这些过渡金属合金形成栅电极的方法。

公开(公告)号：US07531437B2

公开(公告)日：2009-05-12

申请号：US11360269

申请日：2006-02-22

Applicant: Justin K. Brask ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

Inventor： Justin K. Brask ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

IPC: H01L21/3205

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

Abstract translation: 要求保护半导体器件，该半导体器件具有形成在绝缘衬底上的具有顶表面和第一和第二横向相对侧壁的半导体本体。 在半导体本体的顶表面和半导体本体的第一和第二横向相对的侧壁上形成栅极电介质。 然后在半导体主体的顶表面上的栅电介质上形成栅电极，并且与半导体本体的第一和第二横向相对的侧壁上的栅电介质相邻。 栅电极包括直接与栅介电层相邻形成的金属膜。 然后在栅电极的相对侧上的半导体本体中形成一对源区和漏区。

公开(公告)号：US07285829B2

公开(公告)日：2007-10-23

申请号：US10816232

申请日：2004-03-31

Applicant: Brian Doyle ,  Scott A. Hareland ,  Mark Doczy ,  Robert S. Chau

Inventor： Brian Doyle ,  Scott A. Hareland ,  Mark Doczy ,  Robert S. Chau

IPC: H01L29/72

CPC classification number: H01L29/4983 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28105 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/32051 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659

Abstract: A transistor comprising a gate electrode formed on a gate dielectric layer formed on a substrate. A pair of source/drain regions are formed in the substrate on opposite sides of the laterally opposite sidewalls of the gate electrode. The gate electrode has a central portion formed on the gate dielectric layer and over the substrate region between the source and drain regions and a pair sidewall portions which overlap a portion of the source/drain regions wherein the central portion has a first work function and said pair of sidewall portions has a second work function, wherein the second work function is different than the first work function.

Abstract translation: 一种晶体管，包括形成在形成于基板上的栅介质层上的栅电极。 在栅电极的横向相对的侧壁的相对侧上的衬底中形成一对源极/漏极区域。 栅极电极具有形成在栅极介电层上并且在源极和漏极区域之间的衬底区域上的中心部分和与源极/漏极区域的一部分重叠的一对侧壁部分，其中中心部分具有第一功函数和所述 一对侧壁部分具有第二功函数，其中第二功函数不同于第一功函数。

公开(公告)号：US20070069302A1

公开(公告)日：2007-03-29

申请号：US11238445

申请日：2005-09-28

Applicant: Been-Yih Jin ,  Robert Chau ,  Brian Doyle ,  Jack Kavalieros ,  Suman Datta ,  Mark Doczy ,  Matthew Metz ,  Justin Brask

Inventor： Been-Yih Jin ,  Robert Chau ,  Brian Doyle ,  Jack Kavalieros ,  Suman Datta ,  Mark Doczy ,  Matthew Metz ,  Justin Brask

IPC: H01L29/78 ,  H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7851 ,  H01L29/78684

Abstract: A method utilizing a common gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby.

Abstract translation: 利用对pMOS和nMOS晶体管具有单功函数的公共栅电极材料的方法，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。

公开(公告)号：US07195021B2

公开(公告)日：2007-03-27

申请号：US11217008

申请日：2005-08-30

Applicant: Michael Chan ,  Robert Bristol ,  Mark Doczy

Inventor： Michael Chan ,  Robert Bristol ,  Mark Doczy

IPC: B08B6/00

CPC classification number: G21K1/06 ,  B08B7/0057 ,  G03F7/70925 ,  Y10S134/902

Abstract: A method for cleaning optics in a chamber. The method can include introducing a first etchant into a chamber that encloses an optical component and a source of electromagnetic radiation that is suitable for lithography, ionizing the first etchant, and removing debris from a surface of the optical component.

Abstract translation: 一种清洁室内光学元件的方法。 该方法可以包括将第一蚀刻剂引入到包围光学部件的室中，以及适于光刻的电磁辐射源，电离第一蚀刻剂，以及从光学部件的表面去除碎屑。

公开(公告)号：US20070037372A1

公开(公告)日：2007-02-15

申请号：US11581183

申请日：2006-10-13

Applicant: Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Uday Shah ,  Chris Barns ,  Matthew Metz ,  Suman Datta ,  Robert Chau

Inventor： Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Uday Shah ,  Chris Barns ,  Matthew Metz ,  Suman Datta ,  Robert Chau

IPC: H01L21/3205

CPC classification number: H01L21/28194 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7843

Abstract: A sacrificial gate structure, including nitride and fill layers, may be replaced with a metal gate electrode. The metal gate electrode may again be covered with a nitride layer covered by a fill layer. The replacement of the nitride and fill layers may reintroduce strain and provide an etch stop.

Abstract translation: 包括氮化物和填充层的牺牲栅极结构可以被金属栅电极代替。 金属栅电极可以再次被填充层覆盖的氮化物层覆盖。 氮化物和填充层的替换可以重新引入应变并提供蚀刻停止。

公开(公告)号：US20060286755A1

公开(公告)日：2006-12-21

申请号：US11154138

申请日：2005-06-15

Applicant: Justin Brask ,  Robert Chau ,  Suman Datta ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros ,  Amlan Majumdar ,  Matthew Metz ,  Marko Radosavljevic

Inventor： Justin Brask ,  Robert Chau ,  Suman Datta ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros ,  Amlan Majumdar ,  Matthew Metz ,  Marko Radosavljevic

IPC: H01L31/119 ,  H01L31/113 ,  H01L31/062 ,  H01L29/94 ,  H01L29/76 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66818 ,  H01L29/7834 ,  H01L29/7838 ,  H01L29/785 ,  H04B1/3827 ,  Y10S438/926

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Abstract translation: 描述了制造具有减薄沟道区的MOS晶体管的方法。 在去除虚拟栅极之后蚀刻沟道区。 源极和漏极区域具有相对较低的电阻。

公开(公告)号：US20060094180A1

公开(公告)日：2006-05-04

申请号：US10980522

申请日：2004-11-02

Applicant: Mark Doczy ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Suman Datta ,  Robert Chau

Inventor： Mark Doczy ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Suman Datta ,  Robert Chau

IPC: H01L21/8238

CPC classification number: H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/66545

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, forming a barrier layer on the high-k gate dielectric layer, and forming a fully silicided gate electrode on the barrier layer.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成高k栅极电介质层，在高k栅极电介质层上形成阻挡层，并在阻挡层上形成完全硅化的栅电极。

公开(公告)号：US20060051882A1

公开(公告)日：2006-03-09

申请号：US11210220

申请日：2005-08-22

Applicant: Mark Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Adrian Sherrill ,  Markus Kuhn ,  Robert Chau

Inventor： Mark Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Adrian Sherrill ,  Markus Kuhn ,  Robert Chau

IPC: H01L21/00 ,  H01L21/336 ,  H01L21/20

CPC classification number: H01L21/0214 ,  H01L21/02142 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/3144 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/517 ,  H01L29/518

Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.

公开(公告)号：US06953719B2

公开(公告)日：2005-10-11

申请号：US10851360

申请日：2004-05-20

Applicant: Mark Doczy ,  Justin K. Brask ,  Steven J. Keating ,  Chris E. Barns ,  Brian S. Doyle ,  Michael L. McSwiney ,  Jack T. Kavalieros ,  John P. Barnak

Inventor： Mark Doczy ,  Justin K. Brask ,  Steven J. Keating ,  Chris E. Barns ,  Brian S. Doyle ,  Michael L. McSwiney ,  Jack T. Kavalieros ,  John P. Barnak

IPC: H01L21/3213 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/66545 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7833 ,  Y10S438/926

Abstract: At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.