发明申请
- 专利标题: OUTPUT BUFFER CIRCUIT
- 专利标题(中): 输出缓冲电路
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申请号: US11469219申请日: 2006-08-31
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公开(公告)号: US20070080723A1公开(公告)日: 2007-04-12
- 发明人: Youn Joong Lee , Won Tae Choi , Chan Woo Park , Byung Hoon Kim
- 申请人: Youn Joong Lee , Won Tae Choi , Chan Woo Park , Byung Hoon Kim
- 申请人地址: KR GYUNGGI-DO
- 专利权人: SAMSUNG ELECTRO-MECHANICS CO., LTD.
- 当前专利权人: SAMSUNG ELECTRO-MECHANICS CO., LTD.
- 当前专利权人地址: KR GYUNGGI-DO
- 优先权: KR10-2005-0093710 20051006; KR10-2006-0067893 20060720
- 主分类号: H03B1/00
- IPC分类号: H03B1/00
摘要:
Provided is an output buffer circuit having a slew rate increasing part configured with a switching element. The output buffer circuit can obtain an output voltage having a high slew rate even though a smaller amount of a bias current than that required in a conventional output buffer is used. Therefore, the output buffer circuit can reduce power consumption. In the output buffer circuit with a compensation capacitive load, an input part has two input terminal receiving differential input voltage signals, and an output part increases a gain of the differential input voltages. A current source biases the output part, and a slew rate increasing part is connected to the output part and the compensation capacitive load. The slew rate increasing part includes a switching element to increase a slew rate of the output buffer circuit.
公开/授权文献
- US07482845B2 Output buffer circuit 公开/授权日:2009-01-27
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