A duty cycle corrector includes a first controllable delay configured to delay a first signal to provide a second signal, a second controllable delay configured to delay the second signal to provide a third signal, a first fixed delay configured to delay the second signal to provide a fourth signal, a second fixed delay configured to delay the first signal to provide a fifth signal, and a circuit configured to adjust the first controllable delay and the second controllable delay to phase lock the third signal to the fifth signal.