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16 条记录 (耗时 0.016 秒)

    Duty cycle corrector
    1.
    发明申请
    Duty cycle corrector 有权
    占空比校正器

    公开(公告)号：US20060170474A1

    公开(公告)日：2006-08-03

    申请号：US11048185

    申请日：2005-02-01

    申请人： Jung Kim ,  Joonho Kim ,  Alessandro Minzoni

    发明人： Jung Kim ,  Joonho Kim ,  Alessandro Minzoni

    IPC分类号： H03K3/017

    CPC分类号： H03K5/1565

    摘要： A duty cycle corrector comprising a first circuit and a second circuit. The first circuit is configured to receive a clock signal and an inverted clock signal and to obtain a delay signal that indicates a time difference between transitions of the clock signal and the inverted clock signal. The second circuit is configured to receive the clock signal and the inverted clock signal and the delay signal and to delay the clock signal based on the delay signal to provide an output clock signal having substantially a 50% duty cycle.

    摘要翻译： 一种占空比校正器，包括第一电路和第二电路。 第一电路被配置为接收时钟信号和反相时钟信号，并且获得指示时钟信号和反相时钟信号的转变之间的时间差的延迟信号。 第二电路被配置为接收时钟信号和反相时钟信号和延迟信号，并且基于延迟信号延迟时钟信号以提供具有基本上50％占空比的输出时钟信号。

    Duty cycle corrector
    2.
    发明申请
    Duty cycle corrector 审中-公开
    占空比校正器

    公开(公告)号：US20070080731A1

    公开(公告)日：2007-04-12

    申请号：US11247538

    申请日：2005-10-11

    申请人： Jung Kim ,  Alessandro Minzoni ,  Joonho Kim

    发明人： Jung Kim ,  Alessandro Minzoni ,  Joonho Kim

    IPC分类号： H03K3/017

    CPC分类号： H03K5/1565 ,  H03K5/151 ,  H03L7/0812

    摘要： A duty cycle corrector includes a first controllable delay configured to delay a first signal to provide a second signal, a second controllable delay configured to delay the second signal to provide a third signal, a first fixed delay configured to delay the second signal to provide a fourth signal, a second fixed delay configured to delay the first signal to provide a fifth signal, and a circuit configured to adjust the first controllable delay and the second controllable delay to phase lock the third signal to the fifth signal.

    摘要翻译： 占空比校正器包括被配置为延迟第一信号以提供第二信号的第一可控延迟，被配置为延迟第二信号以提供第三信号的第二可控延迟;第一固定延迟，被配置为延迟第二信号以提供第二信号 第四信号，第二固定延迟，被配置为延迟所述第一信号以提供第五信号;以及电路，被配置为调整所述第一可控延迟和所述第二可控延迟以将所述第三信号锁相到所述第五信号。

    Digital duty cycle corrector
    3.
    发明申请
    Digital duty cycle corrector 有权
    数字占空比校正器

    公开(公告)号：US20060001462A1

    公开(公告)日：2006-01-05

    申请号：US10881598

    申请日：2004-06-30

    申请人： Joonho Kim ,  Jung Kim ,  Alessandro Minzoni

    发明人： Joonho Kim ,  Jung Kim ,  Alessandro Minzoni

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0814 ,  H03K5/1565 ,  H03L7/07 ,  H03L7/0805

    摘要： A method for adjusting the relative phases of two signals includes receiving first and second signals, which may, for example, be derived from a differential clock signal. A duty cycle error between the first signal and the second signal is detected by comparing a phase component of the first signal with a phase component of the second signal. This duty cycle error can then be corrected by delaying the second signal by an amount based upon a result derived from the comparing.

    摘要翻译： 用于调整两个信号的相对相位的方法包括接收第一和第二信号，其可以例如从差分时钟信号导出。 通过将第一信号的相位分量与第二信号的相位分量进行比较来检测第一信号和第二信号之间的占空比误差。 然后可以通过基于从比较导出的结果将第二信号延迟量来校正该占空比误差。

    Digital duty cycle corrector
    4.
    发明授权
    Digital duty cycle corrector 有权
    数字占空比校正器

    公开(公告)号：US07187221B2

    公开(公告)日：2007-03-06

    申请号：US10881598

    申请日：2004-06-30

    申请人： Joonho Kim ,  Jung Pill Kim ,  Alessandro Minzoni

    发明人： Joonho Kim ,  Jung Pill Kim ,  Alessandro Minzoni

    IPC分类号： H03K3/017 ,  H03L7/06

    CPC分类号： H03L7/0814 ,  H03K5/1565 ,  H03L7/07 ,  H03L7/0805

    摘要： A method for adjusting the relative phases of two signals includes receiving first and second signals, which may, for example, be derived from a differential clock signal. A duty cycle error between the first signal and the second signal is detected by comparing a phase component of the first signal with a phase component of the second signal. This duty cycle error can then be corrected by delaying the second signal by an amount based upon a result derived from the comparing.

    摘要翻译： 用于调整两个信号的相对相位的方法包括接收第一和第二信号，其可以例如从差分时钟信号导出。 通过将第一信号的相位分量与第二信号的相位分量进行比较来检测第一信号和第二信号之间的占空比误差。 然后可以通过基于从比较导出的结果将第二信号延迟量来校正该占空比误差。

    Duty cycle corrector
    5.
    发明授权
    Duty cycle corrector 有权
    占空比校正器

    公开(公告)号：US07221204B2

    公开(公告)日：2007-05-22

    申请号：US11048185

    申请日：2005-02-01

    申请人： Jung Pill Kim ,  Joonho Kim ,  Alessandro Minzoni

    发明人： Jung Pill Kim ,  Joonho Kim ,  Alessandro Minzoni

    IPC分类号： H03K3/017

    CPC分类号： H03K5/1565

    摘要： A duty cycle corrector comprising a first circuit and a second circuit. The first circuit is configured to receive a clock signal and an inverted clock signal and to obtain a delay signal that indicates a time difference between transitions of the clock signal and the inverted clock signal. The second circuit is configured to receive the clock signal and the inverted clock signal and the delay signal and to delay the clock signal based on the delay signal to provide an output clock signal having substantially a 50% duty cycle.

    摘要翻译： 一种占空比校正器，包括第一电路和第二电路。 第一电路被配置为接收时钟信号和反相时钟信号，并且获得指示时钟信号和反相时钟信号的转变之间的时间差的延迟信号。 第二电路被配置为接收时钟信号和反相时钟信号和延迟信号，并且基于延迟信号延迟时钟信号以提供具有基本上50％占空比的输出时钟信号。

    Duty cycle corrector
    6.
    发明申请
    Duty cycle corrector 有权
    占空比校正器

    公开(公告)号：US20060214714A1

    公开(公告)日：2006-09-28

    申请号：US11442842

    申请日：2006-05-30

    申请人： Joonho Kim ,  Jung Kim ,  Jonghee Han

    发明人： Joonho Kim ,  Jung Kim ,  Jonghee Han

    IPC分类号： H03K3/017

    CPC分类号： G06F1/04 ,  H03K5/1565

    摘要： A duty cycle corrector, including a first, second circuit and a third circuit is disclosed. The third circuit is configured to obtain a threshold value in response to charge flow that is regulated by the first circuit and the second circuit, wherein the first circuit is configured to receive a clock signal and change the charge flow at a first transition of the clock signal. The second circuit is configured to change the charge flow at a second transition of the clock signal. The first circuit and the second circuit are configured to change the charge flow in response to obtaining the threshold value.

    摘要翻译： 公开了包括第一，第二电路和第三电路的占空比校正器。 第三电路被配置为响应于由第一电路和第二电路调节的电荷流量获得阈值，其中第一电路被配置为接收时钟信号并且在时钟的第一转变处改变电荷流 信号。 第二电路被配置为在时钟信号的第二转变处改变电荷流。 第一电路和第二电路被配置为响应于获得阈值来改变电荷流。

    Duty cycle corrector
    7.
    发明申请
    Duty cycle corrector 有权
    占空比校正器

    公开(公告)号：US20060152265A1

    公开(公告)日：2006-07-13

    申请号：US11032459

    申请日：2005-01-10

    申请人： Joonho Kim ,  Jung Kim ,  Jonghee Han

    发明人： Joonho Kim ,  Jung Kim ,  Jonghee Han

    IPC分类号： H03K3/017

    CPC分类号： G06F1/04 ,  H03K5/1565

    摘要： A duty cycle corrector comprising a first circuit and a second circuit. The first circuit is configured to receive a clock signal having a first phase and a second phase and to obtain a first threshold value based on the length of the first phase and part of the second phase and provide a first pulse and response to the first threshold value. The second circuit is configured to receive the clock signal and to obtain a second threshold value based on the length of the second phase and part of the first phase and provide a second pulse in response to the second threshold value. The time between the start of the first pulse and the start of the second pulse is substantially one half clock cycle.

    摘要翻译： 一种占空比校正器，包括第一电路和第二电路。 第一电路被配置为接收具有第一相位和第二相位的时钟信号，并且基于第一相位的长度和第二相位的一部分来获得第一阈值，并且提供第一脉冲和对第一阈值的响应 值。 第二电路被配置为接收时钟信号并且基于第二相位的长度和第一相的一部分获得第二阈值，并且响应于第二阈值提供第二脉冲。 第一脉冲的开始和第二脉冲的开始之间的时间基本上是一个半个时钟周期。