A scan driving circuit including an input terminal to receive an input signal or a voltage output from a previous stage; first and second clock terminals to receive first and second clock signals having phases inverted to each other and partially overlap at a high level, respectively; and a plurality of stages having an output terminal to output scan signals having a low level in sequence, leaving an interval between the scan signals, equivalent to a time the first and second clock signals overlap at the high level, wherein the output terminal of the stage is maintained to have a non-floating state regardless of whether the stage outputs the scan signal.