Invention Application
- Patent Title: FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROBE CARD
- Patent Title (中): 半导体集成电路器件和探针卡的制造方法
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Application No.: US11555993Application Date: 2006-11-02
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Publication No.: US20070108997A1Publication Date: 2007-05-17
- Inventor: Yasuhiro Motoyama , Yoshimi Horigome , Seigo Nakamura , Iwao Natori
- Applicant: Yasuhiro Motoyama , Yoshimi Horigome , Seigo Nakamura , Iwao Natori
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Priority: JP2005-327183 20051111
- Main IPC: G01R31/02
- IPC: G01R31/02

Abstract:
To provide a technique of firmly bringing a stylus and a test pad into contact with each other in carrying out a probe testing summarizingly for plural chips by using a prober having the stylus formed by a technique of manufacturing a semiconductor integrated circuit device, plane patterns of respective wirings are formed such that a wiring and a wiring electrically connected to the wiring or a wiring which is not electrically connected to the wiring overlap each other, and a plane pattern arranged with both of the wiring and the wiring is constituted at upper portions of probes. Further, patterns of the wirings are formed such that an interval of arranging the wirings and a density of arranging the wirings become uniform at respective wiring layers in a thin film sheet.
Public/Granted literature
- US07688086B2 Fabrication method of semiconductor integrated circuit device and probe card Public/Granted day:2010-03-30
Information query