发明申请
US20070113161A1 CASCADED RADIX ARCHITECTURE FOR HIGH-SPEED VITERBI DECODER 审中-公开
用于高速VITERBI解码器的CASCADED RADIX架构

CASCADED RADIX ARCHITECTURE FOR HIGH-SPEED VITERBI DECODER
摘要:
A Viterbi decoder includes a branch metric unit for generating branch metrics between two states at two different time periods, a traceback unit, a traceback memory and an add-compare-select circuit. The add-compare-select circuit includes a plurality of cascaded add-compare-select sub-circuits, each add-compare-select sub-circuit calculating a path metric responsive to a plurality of branch metrics from the branch metric unit and a plurality of pre-calculated path metrics, where at least one of the add-compare-select sub-circuits receives a set of pre-calculated path metrics from another one of the add-compare-select sub-circuits.
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