Invention Application
US20070122982A1 Method of applying stresses to PFET and NFET transistor channels for improved performance
有权
向PFET和NFET晶体管通道施加应力以提高性能的方法
- Patent Title: Method of applying stresses to PFET and NFET transistor channels for improved performance
- Patent Title (中): 向PFET和NFET晶体管通道施加应力以提高性能的方法
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Application No.: US11657154Application Date: 2007-01-24
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Publication No.: US20070122982A1Publication Date: 2007-05-31
- Inventor: Victor Chan , Yong Lee , Haining Yang
- Applicant: Victor Chan , Yong Lee , Haining Yang
- Main IPC: H01L21/8234
- IPC: H01L21/8234

Abstract:
A method is provided for fabricating a semiconductor device structure. In such method a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), each of the NFET and the PFET having a conduction channel disposed in a single-crystal semiconductor region of a substrate. A stressed film having a compressive stress at a first magnitude can be formed to overlie the PFET and the NFET. Desirably, a mask is formed to cover the PFET while exposing the NFET, after which, desirably, a portion of the stressed film overlying the NFET is subjected to ion implantation, while the mask protects another portion of the stressed film overlying the PFET from the ion implantation. The substrate can then be annealed, whereby, desirably, the compressive stress of the implanted portion of the stressed film is much reduced from the first magnitude by the annealing. In such way, the implanted portion of the stressed film overlying the NFET desirably imparts one of a much reduced magnitude compressive stress, a zero stress and a tensile stress to the conduction channel of the NFET. Another portion of the stressed film can continue to impart the compressive stress at the first magnitude to the conduction channel of the PFET.
Public/Granted literature
- US07442611B2 Method of applying stresses to PFET and NFET transistor channels for improved performance Public/Granted day:2008-10-28
Information query
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