公开(公告)号：US20070122982A1

公开(公告)日：2007-05-31

申请号：US11657154

申请日：2007-01-24

申请人： Victor Chan ,  Yong Lee ,  Haining Yang

发明人： Victor Chan ,  Yong Lee ,  Haining Yang

IPC分类号： H01L21/8234

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L29/665

摘要： A method is provided for fabricating a semiconductor device structure. In such method a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), each of the NFET and the PFET having a conduction channel disposed in a single-crystal semiconductor region of a substrate. A stressed film having a compressive stress at a first magnitude can be formed to overlie the PFET and the NFET. Desirably, a mask is formed to cover the PFET while exposing the NFET, after which, desirably, a portion of the stressed film overlying the NFET is subjected to ion implantation, while the mask protects another portion of the stressed film overlying the PFET from the ion implantation. The substrate can then be annealed, whereby, desirably, the compressive stress of the implanted portion of the stressed film is much reduced from the first magnitude by the annealing. In such way, the implanted portion of the stressed film overlying the NFET desirably imparts one of a much reduced magnitude compressive stress, a zero stress and a tensile stress to the conduction channel of the NFET. Another portion of the stressed film can continue to impart the compressive stress at the first magnitude to the conduction channel of the PFET.

摘要翻译： 提供了制造半导体器件结构的方法。 在这种方法中，p型场效应晶体管（PFET）和n型场效应晶体管（NFET），NFET和PFET中的每一个具有设置在基板的单晶半导体区域中的导电沟道。 可以形成具有第一大小的压应力的应力膜覆盖在PFET和NFET上。 期望地，形成掩模以在暴露NFET的同时覆盖PFET，之后理想地，覆盖NFET的应力膜的一部分经受离子注入，而掩模保护覆盖PFET的应力膜的另一部分与 离子注入。 然后可以对衬底进行退火，因此期望地，应力膜的注入部分的压缩应力通过退火从第一量级大大降低。 以这种方式，覆盖NFET的应力膜的注入部分期望地将大大减小的压缩应力，零应力和拉伸应力中的一个施加到NFET的传导通道。 应力膜的另一部分可以继续将第一大小的压应力赋予PFET的传导通道。

公开(公告)号：US20070134870A1

公开(公告)日：2007-06-14

申请号：US11299542

申请日：2005-12-12

申请人： Yong Lee ,  Haining Yang ,  Victor Chan

发明人： Yong Lee ,  Haining Yang ,  Victor Chan

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

摘要： A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second region (e.g., NFET region). A stress layer is over the stress relief layer in the first region and over the devices and substrate/silicide in the second region. The NFET transistor performance is enhanced due to the overall tensile stress in the NFET channel while the degradation in the PFET transistor performance is reduced/eliminated due to the inclusion of the stress relief layer. In a second example embodiment, the stress relief layer is formed over the second region, but not the first region and the stress of the stress layer is reversed.

摘要翻译： 在衬底的一个区域中的应力层下方具有应力消除层的半导体器件的制造结构和方法。 在第一示例中，应力消除层形成在衬底的第一区域（例如，PFET区域）上，而不是在第二区域（例如，NFET区域）之上。 应力层在第一区域中的应力消除层上方和第二区域中的器件和衬底/硅化物之上。 NFET晶体管的性能由于NFET沟道中的整体拉伸应力而增强，而由于包含应力消除层而降低/消除了PFET晶体管性能的降低。 在第二示例性实施例中，应力消除层形成在第二区域上，但不是第一区域并且应力层的应力被反转。

公开(公告)号：US20060228848A1

公开(公告)日：2006-10-12

申请号：US10907415

申请日：2005-03-31

申请人： Victor Chan ,  Haining Yang ,  Yong Lee ,  Eng Lim

发明人： Victor Chan ,  Haining Yang ,  Yong Lee ,  Eng Lim

IPC分类号： H01L21/471

CPC分类号： H01L29/7843 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/78

摘要： Methods of fabricating a semiconductor device including a dual-hybrid liner in which an underlying silicide layer is protected from photoresist stripping chemicals by using a hard mask as a pattern during etching, rather than using a photoresist. The hard mask prevents exposure of a silicide layer to photoresist stripping chemicals and provides very good lateral dimension control such that the two nitride liners are well aligned.

摘要翻译： 制造包括双重混合衬垫的半导体器件的方法，其中通过在蚀刻期间使用硬掩模作为图案来保护底层硅化物层免受光致抗蚀剂剥离化学品，而不是使用光致抗蚀剂。 硬掩模防止硅化物层暴露于光致抗蚀剂剥离化学品，并提供非常好的横向尺寸控制，使得两个氮化物衬垫良好对准。

公开(公告)号：US20060113568A1

公开(公告)日：2006-06-01

申请号：US10904808

申请日：2004-11-30

申请人： Victor Chan ,  Yong Lee ,  Haining Yang

发明人： Victor Chan ,  Yong Lee ,  Haining Yang

IPC分类号： H01L27/10

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L29/665

摘要： A semiconductor device structure is provided which includes a first semiconductor device; a second semiconductor device; and a unitary stressed film disposed over both the first and second semiconductor devices. The stressed film has a first portion overlying the first semiconductor device, the first portion imparting a first magnitude compressive stress to a conduction channel of the first semiconductor device, the stressed film further having a second portion overlying the second semiconductor device, the second portion not imparting the first magnitude compressive stress to a conduction channel of the second semiconductor device, the second portion including an ion concentration not present in the second portion such that the second portion imparts one of a compressive stress having a magnitude much lower than the first magnitude, zero stress, and a tensile stress to the conduction channel of the second semiconductor device.

摘要翻译： 提供一种半导体器件结构，其包括第一半导体器件; 第二半导体器件; 以及设置在第一和第二半导体器件两者上的单一应力膜。 应力膜具有覆盖第一半导体器件的第一部分，第一部分向第一半导体器件的导电通道施加第一大小压缩应力，应力膜还具有覆盖第二半导体器件的第二部分，第二部分不 将第一强度压缩应力施加到第二半导体器件的导电通道，第二部分包括不存在于第二部分中的离子浓度，使得第二部分施加具有远低于第一大小的量级的压缩应力之一， 零应力和对第二半导体器件的导电通道的拉伸应力。

公开(公告)号：US20050093078A1

公开(公告)日：2005-05-05

申请号：US10695754

申请日：2003-10-30

申请人： Victor Chan ,  Haining Yang

发明人： Victor Chan ,  Haining Yang

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/76 ,  H01L31/062

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092

摘要： Enhanced carrier mobility in transistors of differing (e.g. complementary) conductivity types is achieved on a common chip by provision of two or more respective stressed layers, such as etch stop layers, overlying the transistors with stress being wholly or partially relieved in portions of the respective layers, preferably by implantations with heavy ions such as germanium, arsenic, xenon, indium, antimony, silicon, nitrogen oxygen or carbon in accordance with a block-out mask. The distribution and small size of individual areas of such stressed structures also prevents warping or curling of even very thin substrates.

公开(公告)号：US07211869B2

公开(公告)日：2007-05-01

申请号：US11110767

申请日：2005-04-21

申请人： Victor Chan ,  Haining Yang

发明人： Victor Chan ,  Haining Yang

IPC分类号： H01L31/00

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092

摘要： Enhanced carrier mobility in transistors of differing (e.g. complementary) conductivity types is achieved on a common chip by provision of two or more respective stressed layers, such as etch stop layers, overlying the transistors with stress being wholly or partially relieved in portions of the respective layers, preferably by implantations with heavy ions such as germanium, arsenic, xenon, indium, antimony, silicon, nitrogen oxygen or carbon in accordance with a block-out mask. The distribution and small size of individual areas of such stressed structures also prevents warping or curling of even very thin substrates.

摘要翻译： 通过提供两个或更多个相应的应力层（例如覆盖晶体管的相应的应力层，例如蚀刻停止层），在共同的芯片上实现增强的不同（例如互补）导电类型的晶体管中的载流子迁移率，其中应力在相应的部分中被部分地完全或部分缓解 层，优选通过根据阻挡掩模的重离子如锗，砷，氙，铟，锑，硅，氮氧或碳的注入。 这种应力结构的各个区域的分布和小尺寸也防止甚至非常薄的基底的翘曲或卷曲。

公开(公告)号：US20050194596A1

公开(公告)日：2005-09-08

申请号：US11110767

申请日：2005-04-21

申请人： Victor Chan ,  Haining Yang

发明人： Victor Chan ,  Haining Yang

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/10

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092

摘要： Enhanced carrier mobility in transistors of differing (e.g. complementary) conductivity types is achieved on a common chip by provision of two or more respective stressed layers, such as etch stop layers, overlying the transistors with stress being wholly or partially relieved in portions of the respective layers, preferably by implantations with heavy ions such as germanium, arsenic, xenon, indium, antimony, silicon, nitrogen oxygen or carbon in accordance with a block-out mask. The distribution and small size of individual areas of such stressed structures also prevents warping or curling of even very thin substrates.

公开(公告)号：US06939814B2

公开(公告)日：2005-09-06

申请号：US10695754

申请日：2003-10-30

申请人： Victor Chan ,  Haining Yang

发明人： Victor Chan ,  Haining Yang

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L21/31

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092

摘要： Enhanced carrier mobility in transistors of differing (e.g. complementary) conductivity types is achieved on a common chip by provision of two or more respective stressed layers, such as etch stop layers, overlying the transistors with stress being wholly or partially relieved in portions of the respective layers, preferably by implantations with heavy ions such as germanium, arsenic, xenon, indium, antimony, silicon, nitrogen oxygen or carbon in accordance with a block-out mask. The distribution and small size of individual areas of such stressed structures also prevents warping or curling of even very thin substrates.

摘要翻译： 通过提供两个或更多个相应的应力层（例如覆盖晶体管的相应的应力层，例如蚀刻停止层），在共同的芯片上实现增强的不同（例如互补）导电类型的晶体管中的载流子迁移率，其中应力在相应的部分中被部分地完全或部分缓解 层，优选通过根据阻挡掩模的重离子如锗，砷，氙，铟，锑，硅，氮氧或碳的注入。 这种应力结构的各个区域的分布和小尺寸也防止甚至非常薄的基底的翘曲或卷曲。

公开(公告)号：US20070099360A1

公开(公告)日：2007-05-03

申请号：US11163916

申请日：2005-11-03

申请人： Yong Lee ,  Haining Yang

发明人： Yong Lee ,  Haining Yang

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/7843 ,  H01L29/7845

摘要： An integrated circuit is provided that includes a substrate, a p-type field effect transistor, a compressive nitride layer, n-type field effect transistor, a tensile nitride layer, and a mask. The compressive nitride layer induces a first compressive stress in a channel region of the p-type field effect transistor. The tensile nitride layer induces a tensile stress in a channel region of the n-type field effect transistor. The mask is defined over an exposed gate conductor of the n-type field effect transistor. The p-type field effect transistor includes a gate conductor having a metal silicide layer with a volume sufficient to induce a second compressive stress in the channel region of the p-type field effect transistor.

摘要翻译： 提供了一种集成电路，其包括基板，p型场效应晶体管，压缩氮化物层，n型场效应晶体管，拉伸氮化物层和掩模。 压缩氮化物层在p型场效应晶体管的沟道区域中引起第一压缩应力。 拉伸氮化物层在n型场效应晶体管的沟道区域中引起拉伸应力。 掩模限定在n型场效应晶体管的暴露的栅极导体上。 p型场效应晶体管包括具有足以在p型场效应晶体管的沟道区域中引起第二压缩应力的金属硅化物层的栅极导体。

公开(公告)号：US20060151843A1

公开(公告)日：2006-07-13

申请号：US10905580

申请日：2005-01-12

申请人： Haining Yang ,  Xiangdong Chen ,  Yong Lee ,  Wenhe Lin

发明人： Haining Yang ,  Xiangdong Chen ,  Yong Lee ,  Wenhe Lin

IPC分类号： H01L29/94

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/1033 ,  H01L29/4933 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843

摘要： A method of reducing hot carrier degradation and a semiconductor structure so formed are disclosed. One embodiment of the method includes depositing a silicon nitride layer over a transistor device, ion implanting a species into the silicon nitride layer to drive hydrogen from the silicon nitride layer, and annealing to diffuse the hydrogen into a channel region of the transistor device. The species may be chosen from, for example: germanium (Ge), arsenic (As), xenon (Xe), nitrogen (N), oxygen (O), carbon (C), boron (B), indium (In), argon (Ar), helium (He), and deuterium (De). The ion implantation modulates atoms in the silicon nitride layer such as hydrogen, nitrogen and hydrogen-nitrogen bonds such that hydrogen can be controllably diffused into the channel region.

摘要翻译： 公开了减少热载流子劣化的方法和如此形成的半导体结构。 该方法的一个实施例包括在晶体管器件上沉积氮化硅层，将物质离子注入到氮化硅层中以从氮化硅层驱动氢，以及退火以将氢扩散到晶体管器件的沟道区域。 该物质可以选自例如：锗（Ge），砷（As），氙（Xe），氮（N），氧（O），碳（C），硼（B），铟（In） 氩（Ar），氦（He）和氘（De）。 离子注入调节氮化硅层中的原子，例如氢，氮和氢 - 氮键，使得氢可以可控地扩散到沟道区中。