Invention Application
- Patent Title: Capacitance laminate and printed circuit board apparatus and method
- Patent Title (中): 电容层压板和印刷电路板装置及方法
-
Application No.: US11323515Application Date: 2005-12-30
-
Publication No.: US20070151758A1Publication Date: 2007-07-05
- Inventor: Gregory Dunn , Jaroslaw Magera , Jovica Savic
- Applicant: Gregory Dunn , Jaroslaw Magera , Jovica Savic
- Main IPC: H05K1/11
- IPC: H05K1/11 ; H01R12/04

Abstract:
A method is for fabricating an embedded capacitance printed circuit board assembly (400, 1100). The embedded capacitance printed circuit board assembly includes two embedded capacitance structures (110). Each capacitance structure (110) includes a crystallized dielectric oxide layer (115) sandwiched between an outer electrode layer (120) and an inner electrode layer (125) in which the two inner electrode layers are electrically connected together. A rivet via (1315) and a stacked via (1110) formed from a button via (910) and a stacked blind via (1111) may be used to electrically connect the two inner electrode layers together. A spindle via (525) may be formed through the inner and outer layers. The multi-layer printed circuit board may be formed from a capacitive laminate (100) that includes two capacitance structures.
Public/Granted literature
- US07361847B2 Capacitance laminate and printed circuit board apparatus and method Public/Granted day:2008-04-22
Information query