公开(公告)号：US20070139864A1

公开(公告)日：2007-06-21

申请号：US11316087

申请日：2005-12-21

Applicant: Gregory Dunn ,  Remy Chelini ,  Robert Croswell ,  Philip Lessner ,  Michael Prevallet ,  John Prymak

Inventor： Gregory Dunn ,  Remy Chelini ,  Robert Croswell ,  Philip Lessner ,  Michael Prevallet ,  John Prymak

IPC: H01G9/00

CPC classification number: H01G9/045 ,  H01G9/0032 ,  H01G9/055 ,  H01G9/15 ,  H05K1/162 ,  H05K3/383 ,  H05K3/429 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2203/0315

Abstract: Embedded capacitors comprise a bimetal foil (500) that includes a first copper layer (205) and an aluminum layer (210) on the first copper layer. The aluminum layer has a smooth side adjacent the first copper layer and a high surface area textured side (215) opposite the first copper layer. The bimetal foil further includes an aluminum oxide layer (305) on the high surface area textured side of the aluminum layer, a conductive polymerlayer (420) on the aluminum oxide layer, and a second copper layer (535) overlying the aluminum oxide layer. The bimetal foil may be embedded in a circuit board (700) to form high value embedded capacitors.

Abstract translation: 嵌入式电容器包括在第一铜层上包括第一铜层（205）和铝层（210）的双金属箔（500）。 铝层具有邻近第一铜层的平滑侧面和与第一铜层相对的高表面积纹理化侧面（215）。 双金属箔还包括在铝层的高表面积纹理化侧的氧化铝层（305），氧化铝层上的导电聚合物层（420）和覆盖在氧化铝层上的第二铜层（535）。 双金属箔可以嵌入在电路板（700）中以形成高价值的嵌入式电容器。

公开(公告)号：US20050133872A1

公开(公告)日：2005-06-23

申请号：US10743589

申请日：2003-12-22

Applicant: Gregory Dunn ,  Scott Carney ,  Jovica Savic

Inventor： Gregory Dunn ,  Scott Carney ,  Jovica Savic

IPC: H01C1/148 ,  H01C7/00 ,  H01C17/065 ,  H01L21/8222 ,  H01L23/498 ,  H01L23/62

CPC classification number: H01C7/006 ,  H01C1/148 ,  H01C17/065 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A technique for fabricating a patterned resistor on a substrate produces a patterned resistor (101, 801, 1001, 1324, 1374) including two conductive end terminations (110, 810, 1010) on the substrate, a pattern of first resistive material (120, 815, 1015) having a first width (125) and a first sheet resistance, and a pattern of second resistive material (205, 820, 1020) having a second width (210) and a second sheet resistance that at least partially overlies the pattern of first resistive material. One of the first and second sheet resistances is a low sheet resistance and the other of the first and second resistances is a high sheet resistance. A ratio of the high sheet resistance to the low sheet resistance is at least ten to one. The pattern having the higher sheet resistance is substantially wider than the pattern having the low sheet resistance. The patterned resistor can be precision trimmed 1225.

Abstract translation: 用于在衬底上制造图案化电阻器的技术产生包括在衬底上的两个导电端接（110,810,1010）的图案化电阻器（101,801,1001,1324,1374），第一电阻材料（120， 具有第一宽度（125）和第一薄层电阻的第二电阻材料（205,820,1020）的图案，以及具有至少部分地覆盖图案的第二宽度（210）和第二薄层电阻的图案 的第一电阻材料。 第一和第二薄层电阻之一是低的薄层电阻，第一和第二电阻中的另一个是高的薄层电阻。 高薄层电阻与低薄层电阻的比例至少为10比1。 具有较高薄层电阻的图案基本上比具有低薄层电阻的图案更宽。 图案化电阻器可精密修整1225。

公开(公告)号：US20050104207A1

公开(公告)日：2005-05-19

申请号：US10982432

申请日：2004-11-05

Applicant: Timothy Dean ,  Terance Blake ,  Gregory Dunn ,  Remy Chelini ,  William Lytle ,  Owen Fay ,  George Strumberger

Inventor： Timothy Dean ,  Terance Blake ,  Gregory Dunn ,  Remy Chelini ,  William Lytle ,  Owen Fay ,  George Strumberger

IPC: H01L23/485 ,  H01L21/44 ,  H01L21/48

CPC classification number: H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/05644 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48644 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/8501 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/16151 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/48744

Abstract: The invention provides an integrated device with corrosion-resistant capped bond pads. The capped bond pads include at least one aluminum bond pad on a semiconductor substrate. A layer of electroless nickel is disposed on the aluminum bond pad. A layer of electroless palladium is disposed on the electroless nickel, and a layer of immersion gold is disposed on the electroless palladium. A capped bond pad and a method of forming the capped bond pads are also disclosed.

公开(公告)号：US20050001324A1

公开(公告)日：2005-01-06

申请号：US10610745

申请日：2003-07-01

Applicant: Gregory Dunn ,  Owen Fay ,  Timothy Dean ,  Terance Blake ,  Remy Chelini ,  William Lytle ,  George Strumberger

Inventor： Gregory Dunn ,  Owen Fay ,  Timothy Dean ,  Terance Blake ,  Remy Chelini ,  William Lytle ,  George Strumberger

IPC: G01L9/00 ,  H01L21/60 ,  H01L23/485 ,  H01L23/498 ,  H01L23/48

CPC classification number: H01L24/12 ,  G01L19/0069 ,  G01L19/147 ,  H01L23/498 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48644 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/85013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012

Abstract: The invention provides an integrated device with corrosion-resistant capped copper bond pads. The capped copper bond pads include at least one copper bond pad on a semiconductor substrate. An activation layer comprising one of immersion palladium, electroless cobalt, or immersion ruthernium is disposed on the copper bond pad. A first intermediate layer of electroless nickel-boron alloy is disposed on the activation layer. A second intermediate layer comprising one of electroless nickel or electroless palladium is disposed on the first intermediate layer, and an immersion gold layer is disposed on the second intermediate layer. A capped copper bond pad and a method of forming the capped copper bond pads are also disclosed.

Abstract translation: 本发明提供了一种具有耐腐蚀的封盖铜焊盘的集成器件。 封装的铜键合焊盘包括半导体衬底上的至少一个铜焊盘。 包含浸渍钯，无电解钴或浸渍铯中的一种的活化层设置在铜键合焊盘上。 化学镀镍 - 硼合金的第一中间层设置在活化层上。 在第一中间层上设置包含非电解镍或无电解钯中的一种的第二中间层，在第二中间层上设置浸金层。 还公开了封盖铜键合焊盘和形成封盖铜键合焊盘的方法。

公开(公告)号：US20070151758A1

公开(公告)日：2007-07-05

申请号：US11323515

申请日：2005-12-30

Applicant: Gregory Dunn ,  Jaroslaw Magera ,  Jovica Savic

Inventor： Gregory Dunn ,  Jaroslaw Magera ,  Jovica Savic

IPC: H05K1/11 ,  H01R12/04

CPC classification number: H05K1/162 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09718

Abstract: A method is for fabricating an embedded capacitance printed circuit board assembly (400, 1100). The embedded capacitance printed circuit board assembly includes two embedded capacitance structures (110). Each capacitance structure (110) includes a crystallized dielectric oxide layer (115) sandwiched between an outer electrode layer (120) and an inner electrode layer (125) in which the two inner electrode layers are electrically connected together. A rivet via (1315) and a stacked via (1110) formed from a button via (910) and a stacked blind via (1111) may be used to electrically connect the two inner electrode layers together. A spindle via (525) may be formed through the inner and outer layers. The multi-layer printed circuit board may be formed from a capacitive laminate (100) that includes two capacitance structures.

Abstract translation: 一种用于制造嵌入式电容印刷电路板组件（400,1100）的方法。 嵌入式电容印刷电路板组件包括两个嵌入式电容结构（110）。 每个电容结构（110）包括夹在两个内部电极层电连接在一起的外部电极层（120）和内部电极层（125）之间的结晶化电介质氧化物层（115）。 可以使用铆钉通孔（1315）和由按钮通孔（910）和堆叠的通孔（1111）形成的堆叠通孔（1110）将两个内部电极层电连接在一起。 主轴通孔（525）可以通过内层和外层形成。 多层印刷电路板可以由包括两个电容结构的电容层压板（100）形成。

公开(公告)号：US20070139294A1

公开(公告)日：2007-06-21

申请号：US11312286

申请日：2005-12-20

Applicant: Gregory Dunn ,  Robert Croswell ,  George Kumpf ,  John Svigelj

Inventor： Gregory Dunn ,  Robert Croswell ,  George Kumpf ,  John Svigelj

IPC: H01Q15/24

CPC classification number: H01Q15/006 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/0715 ,  H05K2201/09509 ,  H05K2201/09609

Abstract: A high impedance surface (300) has a printed circuit board (302) with a first surface (314) and a second surface (316), and a continuous electrically conductive plate (319) disposed on the second surface (316) of the printed circuit board (302). A plurality of electrically conductive plates (318) is disposed on the first surface (314) of the printed circuit board (302), while a plurality of elements are also provided. Each element comprises at least one of (1) at least one multi-layer inductor (330, 331) electrically coupled between at least two of the electrically conductive plates (318) and embedded within the printed circuit board (302), and (2) at least one capacitor (320) electrically coupled between at least two of the electrically conductive plates (318). The capacitor (320) comprises at least one of (a) a dielectric material (328) disposed between adjacent electrically conductive plates , wherein the dielectric material (328) has a relative dielectric constant greater than 6, and (b) a mezzanine capacitor embedded within the printed circuit board (302).

Abstract translation: 高阻抗表面（300）具有带有第一表面（314）和第二表面（316）的印刷电路板（302）和设置在印刷的第二表面（316）上的连续导电板（319） 电路板（302）。 多个导电板（318）设置在印刷电路板（302）的第一表面（314）上，同时还提供多个元件。 每个元件包括（1）至少一个电耦合在至少两个导电板（318）之间并嵌入印刷电路板（302）内的多层电感器（330,331）中的至少一个，和（2 ）至少一个电耦合在至少两个导电板（318）之间的电容器（320）。 电容器（320）包括设置在相邻导电板之间的（a）介电材料（328）中的至少一个，其中介电材料（328）具有大于6的相对介电常数，以及（b）嵌入的夹层电容器 在印刷电路板（302）内。

公开(公告)号：US20060137173A1

公开(公告)日：2006-06-29

申请号：US11021444

申请日：2004-12-23

Applicant: Gregory Dunn ,  Jovica Savic ,  John Svigelj ,  Nadia Yala

Inventor： Gregory Dunn ,  Jovica Savic ,  John Svigelj ,  Nadia Yala

IPC: H01P11/00 ,  H01K3/10

CPC classification number: H01Q9/0407 ,  Y10T29/49016 ,  Y10T29/49117 ,  Y10T29/49165

Abstract: A textured dielectric panel (305, 520, 625, 745, 925, 1035, 1205) is fabricated by applying a first mask pattern (310, 510, 610, 710, 915, 1015, 1210) to a first side of a solid panel made of a first material that is a ceramic dielectric and then sandblasting the solid panel through the first mask pattern from the first side to at least partially generate a shaped cavity (315, 920, 1040). The shaped cavity of the solid panel may be filled with a-second material (330, 740). The first and second materials have substantially differing dielectric constants. The first side and second side of the solid panel may be metallized (325), forming a patch antenna. The shaped cavities can be made more complex by using additional masking and/or sandblasting steps.

Abstract translation: 通过将第一掩模图案（310,510,610,710,915,1015,1210）施加到固体面板的第一侧来制造纹理化电介质面板（305,520,625,745,925,1035,1205） 由第一材料制成，其是陶瓷电介质，然后通过第一掩模图案从第一侧喷砂固体板，以至少部分地产生成型腔（315,920,1040）。 固体面板的成形腔可以填充有第二材料（330,740）。 第一和第二材料具有基本上不同的介电常数。 固体面板的第一面和第二面可以金属化（325），形成贴片天线。 通过使用额外的掩模和/或喷砂步骤，可使成形的空腔变得更加复杂。

公开(公告)号：US06256866B1

公开(公告)日：2001-07-10

申请号：US09309457

申请日：1999-05-11

Applicant: Gregory Dunn

Inventor： Gregory Dunn

IPC: H01C1728

CPC classification number: H05K1/167 ,  H01C1/14 ,  H01C7/005 ,  H01C17/281 ,  H05K1/095 ,  H05K3/0023 ,  H05K3/243 ,  H05K3/4664 ,  H05K2203/1453 ,  H05K2203/1461 ,  Y10T29/49099 ,  Y10T29/49101 ,  Y10T29/49128 ,  Y10T29/49156

Abstract: A method of manufacturing a printed circuit board with a polymer thick-film (PTF) resistor whose dimensions can be defined with improved precision by providing a circuit board construction having a planar surface where the resistor is to be deposited. To achieve the desired board construction, the interconnect for the resistor is pattern plated using a permanent photodielectric layer as a plating mask instead of a sacrificial plating resist. The interconnect can be patterned before or after the PTF resistor ink is printed. The x and z dimensions (width and thickness, respectively) of the resistor are determined by the deposition process, while the y dimension (electrical length) is accurately determined by copper terminations.

公开(公告)号：US20080216296A1

公开(公告)日：2008-09-11

申请号：US12031092

申请日：2008-02-14

Applicant: John D. Prymak ,  Chris Stolarski ,  David Jacobs ,  Chris Wayne ,  Philip Lessner ,  John T. Kinard ,  Alethia Melody ,  Gregory Dunn ,  Robert T. Croswell ,  Remy J. Chelini

Inventor： John D. Prymak ,  Chris Stolarski ,  David Jacobs ,  Chris Wayne ,  Philip Lessner ,  John T. Kinard ,  Alethia Melody ,  Gregory Dunn ,  Robert T. Croswell ,  Remy J. Chelini

IPC: H01G4/002

CPC classification number: H01G9/0029 ,  H01G9/012 ,  H01G9/0425 ,  H01G9/055 ,  H01G9/15 ,  H05K1/185 ,  Y10T29/417

Abstract: An improved method for forming a capacitor. The method includes the steps of: providing a metal foil; forming a dielectric on the metal foil; applying a non-conductive polymer dam on the dielectric to isolate discrete regions of the dielectric; forming a cathode in at least one discrete region of the discrete regions on the dielectric; and cutting the metal foil at the non-conductive polymer dam to isolate at least one capacitor comprising one cathode, one discrete region of the dielectric and a portion of the metal foil with the discrete region of the dielectric.

Abstract translation: 一种形成电容器的改进方法。 该方法包括以下步骤：提供金属箔; 在金属箔上形成电介质; 将非导电聚合物坝施加在电介质上以隔离电介质的离散区域; 在电介质上的离散区域的至少一个离散区域中形成阴极; 并且在非导电聚合物阻挡件处切割金属箔以将包括一个阴极，电介质的一个离散区域和金属箔的一部分的至少一个电容器与电介质的离散区域隔离。

公开(公告)号：US20070209178A1

公开(公告)日：2007-09-13

申请号：US11276688

申请日：2006-03-10

Applicant: Jovica Savic ,  Remy Chelini ,  Gregory Dunn

Inventor： Jovica Savic ,  Remy Chelini ,  Gregory Dunn

IPC: H01G7/00 ,  H01K3/10

CPC classification number: H01G4/33 ,  H01G4/12 ,  H05K1/162 ,  H05K3/0044 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2203/025 ,  Y10T29/417 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for forming embedded capacitors on a printed circuit board is disclosed. The capacitor is formed on the printed circuit board by a depositing a first dielectric layer over one or more electrodes situated on the PCB. Another electrode is formed on top of the first dielectric layer and a second dielectric layer is deposited on top of that electrode. A third electrode is formed on top of the second dielectric layer. The two dielectric layers are abrasively delineated in a single step by a method such as sand blasting to define portions of the first and second dielectric layers to create a multilayer capacitive structure.

Abstract translation: 公开了一种在印刷电路板上形成嵌入式电容器的方法。 通过在位于PCB上的一个或多个电极上沉积第一介电层，在印刷电路板上形成电容器。 另一电极形成在第一电介质层的顶部，并且第二电介质层沉积在该电极的顶部上。 在第二电介质层的顶部形成第三电极。 通过诸如喷砂的方法在单个步骤中擦拭两个电介质层，以限定第一和第二电介质层的部分以产生多层电容结构。