发明申请
- 专利标题： In-situ deposition for cu hillock suppression
- 专利标题（中）： 原位沉积用于小丘抑制
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申请号： US11334849申请日： 2006-01-19
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公开(公告)号： US20070164439A1公开(公告)日： 2007-07-19
- 发明人: Chung-Hsien Chen , Chun-Chieh Lin , Minghsing Tsai , Shau-Lin Shue
- 申请人： Chung-Hsien Chen , Chun-Chieh Lin , Minghsing Tsai , Shau-Lin Shue
- 专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 主分类号： H01L23/48
- IPC分类号： H01L23/48
摘要：
A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than about two.
公开/授权文献
- US07423347B2 In-situ deposition for cu hillock suppression 公开/授权日：2008-09-09
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