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    GAP FILLING METHOD FOR DUAL DAMASCENE PROCESS
    1.
    发明申请
    GAP FILLING METHOD FOR DUAL DAMASCENE PROCESS 有权
    GAP填充方法双重DAMASCENE过程

    公开(公告)号：US20120319278A1

    公开(公告)日：2012-12-20

    申请号：US13161701

    申请日：2011-06-16

    Applicant: Chun-Chieh Lin ,  Hung-Wen Su ,  Minghsing Tsai ,  Syun-Ming Jang

    Inventor： Chun-Chieh Lin ,  Hung-Wen Su ,  Minghsing Tsai ,  Syun-Ming Jang

    IPC: H01L23/48 ,  H01L21/768

    CPC classification number: H01L21/76877 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/511 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.

    Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括形成具有多个第一开口的图案化电介质层。 该方法包括在图案化的介电层上形成导电衬垫层，导电衬垫层部分填充第一开口。 该方法包括在第一开口之外的导电衬垫层的部分上形成沟槽掩模层，从而形成多个第二开口，其中一部分形成在第一开口上。 该方法包括在第一开口中沉积导电材料以形成多个通孔，并且在第二开口中形成多个金属线。 该方法包括去除沟槽掩模层。

    Inflected magnetoresistive structures and memory cells having inflected magnetoresistive structures
    2.
    发明授权
    Inflected magnetoresistive structures and memory cells having inflected magnetoresistive structures 失效
    具有变形磁阻结构的变形磁阻结构和存储单元

    公开(公告)号：US07705340B2

    公开(公告)日：2010-04-27

    申请号：US11163118

    申请日：2005-10-05

    Applicant: Chun-Chieh Lin

    Inventor： Chun-Chieh Lin

    IPC: H01L47/00

    CPC classification number: H01L27/228 ,  H01L43/08

    Abstract: Disclosed herein is a magnetoresistive structure having a non-planar form. Embodiments of the present MR structure includes those having at least one inflection between a first portion of the MR structure that is somewhat vertical relative to a substrate and a second portion of the MR structure that is somewhat horizontal relative to the substrate. Such a structure can be used for memory device, for example an MRAM memory device, wherein the memory density is increased compared to devices having prior planar MR structures without reducing the surface area of the MR structures.

    Abstract translation: 本文公开了具有非平面形式的磁阻结构。 本发明的MR结构的实施例包括那些在MR结构的第一部分之间相对于衬底稍微垂直的第一部分和MR结构相对于衬底稍微水平的第二部分的至少一个拐点。 这种结构可以用于存储器件，例如MRAM存储器件，其中与具有先前的平面MR结构的器件相比，存储器密度增加而不减小MR结构的表面积。

    Web camera
    3.
    发明授权
    Web camera 有权
    网络摄像头

    公开(公告)号：US07656433B2

    公开(公告)日：2010-02-02

    申请号：US11707967

    申请日：2007-02-20

    Applicant: Chi-Hsien Wang ,  Wen-Ming Huang ,  Wei-Song Yeh ,  Chun-Chieh Lin ,  Kuan-Chou Chen

    Inventor： Chi-Hsien Wang ,  Wen-Ming Huang ,  Wei-Song Yeh ,  Chun-Chieh Lin ,  Kuan-Chou Chen

    IPC: H04N5/228 ,  H04N5/225 ,  H04N7/26

    CPC classification number: H04N19/184 ,  H04N19/91

    Abstract: A web camera includes an image sensor, which takes an external image; a sensor interface, which is connected to the mage sensor to receive and convert the image taken by the image sensor into digital image data; at least one compression module, which is connected to the sensor interface to receive and compress the digital image data into compressed image data; and a USB interface, which is connected to the compression module to output the compressed image data to a host device having a USB interface port, such as a computer and a USB OTG device, for storage, playing back and other applications.

    Abstract translation: 网络摄像机包括拍摄外部图像的图像传感器; 传感器接口，其连接到法师传感器，以将图像传感器拍摄的图像接收并转换为数字图像数据; 至少一个压缩模块，其连接到传感器接口以将数字图像数据接收并压缩成压缩图像数据; 以及USB接口，其连接到压缩模块以将压缩的图像数据输出到具有诸如计算机和USB OTG设备的USB接口端口的主机设备，用于存储，回放和其他应用。

    Systems and methods for buffering articles in transport
    5.
    发明申请
    Systems and methods for buffering articles in transport 审中-公开
    运输中缓冲物品的系统和方法

    公开(公告)号：US20090000908A1

    公开(公告)日：2009-01-01

    申请号：US12218625

    申请日：2008-07-15

    Applicant: Michael D. Brain ,  Chun-Chieh Lin

    Inventor： Michael D. Brain ,  Chun-Chieh Lin

    IPC: B65G49/07 ,  G06F7/00

    CPC classification number: B65G37/005 ,  B65G37/02 ,  B65G2201/0297 ,  H01L21/67276 ,  H01L21/67715 ,  H01L21/67769

    Abstract: A system for buffering articles in transport is provided. The system comprises a buffer module configured to buffer articles and a computing system. The buffer module includes a first conveyor configured to transport the articles and a transference node configured to transfer the articles between the first conveyor and an external location. The computing system is configured to maintain an inventory list including a present location of each of the articles buffered by the buffer module. The computing system is further configured to control operation of the buffer module to transfer a selected article among the buffered articles to the external location.

    Abstract translation: 提供了一种用于在运输中缓冲物品的系统。 该系统包括被配置为缓冲物品和计算系统的缓冲模块。 缓冲器模块包括构造成输送物品的第一传送器和被配置成在第一传送器和外部位置之间传送物品的传送节点。 计算系统被配置为维护包括由缓冲器模块缓冲的每个文章的当前位置的清单列表。 计算系统还被配置为控制缓冲器模块的操作以将缓冲的物品中的所选物品传送到外部位置。

    Strained-channel semiconductor structure and method for fabricating the same
    8.
    发明授权
    Strained-channel semiconductor structure and method for fabricating the same 有权
    应变通道半导体结构及其制造方法

    公开(公告)号：US07381604B2

    公开(公告)日：2008-06-03

    申请号：US11423457

    申请日：2006-06-12

    Applicant: Chun-Chieh Lin ,  Yee-Chia Yeo

    Inventor： Chun-Chieh Lin ,  Yee-Chia Yeo

    IPC: H01L21/336

    CPC classification number: H01L21/823425 ,  H01L21/76224 ,  H01L21/823412 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7848

    Abstract: A strained-channel semiconductor structure and method of fabricating the same. The strained-channel semiconductor structure comprises a substrate composed of a first semiconductor material with a first natural lattice constant. A channel region is disposed in the substrate and a gate stack is disposed over the strained channel region. A pair of source/drain regions are oppositely disposed in the substrate adjacent to the channel region, wherein each of the source/drain regions comprises a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant rather than the first natural lattice constant, an inner side and an outer side corresponding to the gate stack, and at least one outer sides laterally contacts the first semiconductor material of the substrate.

    Abstract translation: 应变通道半导体结构及其制造方法。 应变通道半导体结构包括由具有第一自然晶格常数的第一半导体材料构成的衬底。 通道区域设置在衬底中，并且栅堆叠设置在应变通道区域上。 一对源极/漏极区域相邻地设置在衬底中，与沟道区域相邻，其中源极/漏极区域中的每个源极/漏极区域包括具有第二自然晶格常数而不是第一自然晶格的第二半导体材料的晶格失配区域 常数，对应于栅极叠层的内侧和外侧，并且至少一个外侧横向接触基板的第一半导体材料。

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