Invention Application
- Patent Title: Wafer level chip scale package having a gap and method for manufacturing the same
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Application No.: US11717691Application Date: 2007-03-14
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Publication No.: US20070176290A1Publication Date: 2007-08-02
- Inventor: Myeong-Soon Park , Hyun-Soo Chung , In-Young Lee , Jae-Sik Chung , Sung-Min Sim , Dong-Hyeon Jang , Young-Hee Song , Seung-Kwan Ryu
- Applicant: Myeong-Soon Park , Hyun-Soo Chung , In-Young Lee , Jae-Sik Chung , Sung-Min Sim , Dong-Hyeon Jang , Young-Hee Song , Seung-Kwan Ryu
- Priority: KR10/2005-0023746 20050322
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/44
Abstract:
A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.
Public/Granted literature
- US07312143B2 Wafer level chip scale package having a gap and method for manufacturing the same Public/Granted day:2007-12-25
Information query
IPC分类:
